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Fin type transistor

A fin structure, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of reduced reliability and yield, reduced performance, and large height changes

Inactive Publication Date: 2015-04-15
GLOBALFOUNDRIES SINGAPORE PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, traditional fin transistors exhibit high parasitic junction capacitance, which degrades performance
In addition, the traditional process of forming fin transistors results in large height variations, which cause device characteristics to vary across the wafer, reducing reliability and yield

Method used

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Embodiment Construction

[0019] Embodiments generally relate to devices, such as semiconductor devices or integrated circuits. In particular, some embodiments relate to transistors used to form integrated circuits. The integrated circuit may be any type of integrated circuit. For example, the integrated circuit may be a dynamic or static random access memory, a signal processor, or a system on chip (SoC) device. The integrated circuit can be incorporated into, for example, consumer electronic products such as computers, mobile phones and personal digital assistants (PDAs). The invention is also applicable to other types of devices or products.

[0020] Figures 1a to 1c Different views of device 100 are shown. Figure 1a shows the top view of the device, Figure 1b A three-dimensional view of the device along A-A' is shown, Figure 1c A cross-sectional view of the device along B-B' is shown. For example, the device includes an integrated circuit. Other types of devices may also be used. refer ...

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PUM

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Abstract

A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S / D regions to reduce parasitic capacitance to improve its performance.

Description

[0001] Cross References to Related Applications [0002] This application is cross-referenced to concurrently filed U.S. Patent Application (Application No. ________; Attorney Docket No. CSM P 2010 NAT 09 US0) entitled "FINFET WITHSTRESSORS" of the same assignee as this application, the contents of which are incorporated by reference this application. Background technique [0003] The industry is already researching fin transistors for next-generation devices, such as technologies below 22nm. This may be due to, for example, fin transistors contributing to high integration density. However, conventional fin transistors exhibit high parasitic junction capacitance, which degrades performance. In addition, the conventional process for forming fin transistors results in large height variations that cause device characteristics to vary across the wafer, reducing reliability and yield. [0004] Accordingly, there is a need to provide fin devices with improved performance and redu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/78603H01L29/785H01L29/66795H01L29/0847
Inventor 卓荣发J·G·李陈忠锋郭克文
Owner GLOBALFOUNDRIES SINGAPORE PTE LTD