Low power-consumption implementation method for CSA3 (Common Scrambling Algorithm 3) descrambling algorithm modules in DVB (Digital Video Broadcasting) system

Abstract

The invention discloses a low power-consumption implementation method for CSA3 descrambling algorithm modules in a DVB system, which includes the following steps: registers are respectively arranged on two deceleration logic input ends in each CSA3 descrambling algorithm module; two isolated deceleration logic calculation paths are set as multi-cycle paths, so that two deceleration logics are isolated in the two different multi-cycle paths; and when the master CSA3 descrambling algorithm module and the slave CSA3 descrambling algorithm module with priority lower than the priory of the master CSA3 descrambling algorithm module in the DVB system operate at the same time, each CSA3 descrambling algorithm module automatically adjusts the operating state of self according to the operating state of the other CSA3 descrambling algorithm module to pause and start the operation of self, so that the power consumption peaks of the two CSA3 descrambling algorithm modules can be staggered. Because the low power-consumption implementation method isolates the two deceleration logics in the two multi-cycle paths, the power consumption of the CSA3 descrambling algorithm modules is reduced, and moreover, the low power-consumption implementation method effectively solves the problems in time sequence and wiring, which exist when the CSA3 descrambling algorithm modules are implemented by hardware.

Description

technical field [0001] The invention belongs to the field of digital television conditional access, in particular to a method for realizing low power consumption of a CSA3 descrambling algorithm module in a DVB system. Background technique [0002] The rapid development and wide application of digital transmission technology, emerging transmission methods such as the Internet and computers, and multimedia terminals have greatly expanded the scope of broadcasting, film and television content. A series of problems have greatly reduced the value of commercial reuse, resulting in frequent violations of the rights and interests of content providers, seriously dampening their enthusiasm for promoting digital TV, and further damaging the rights and interests of viewers to enjoy high-quality programs, affecting the health of the current digital TV overall conversion develop. [0003] The piracy and infringement of digital radio, film and television content have attracted worldwide ...

AI Technical Summary

Problems solved by technology

[0013] 1. Whether it is the calculation path of even-numbered iterations or the calculation path of odd-numbered iterations, there is a problem of large path delay

[0014] 2. Due to the complexity of the algorithm, the two delay logics A and B have the problem of tight wiring

The two problems of wiring and timing are intertwined, which increases the difficulty of solving the problem, which may lead to too large wiring resources, a sharp increase in wiring area, and may even lead to the consequences of wiring failure

[0015] 3. In figure 2 In the structure, there is a timing loop, which reduces the test coverage of the circuit

[0016] 4. In figure 2 In the calculation path of , because the data path is too long, there are many signal reversals in the combinational logic during work, and it takes a long time for the input terminals of the two modules A and B to stabilize, so that there will be many signals at the input terminals of the two modules A and B Invalid Signal Toggle

In the calculation path of "delay logic Aà contraction function Dà expansion function Eà delay logic Bà contraction function C", the logic delay B will cause a sharp increase in power consumption due to too many signal inversions during the operation; in the "delay logic Bà contraction function Dà In the calculation path of expansion function E→delay logic A→shrink function C”, the logic delay A will cause a sharp increase in power consumption due to too many signal flips during the operation

Moreover, the power consumption of the two logic delays A and B may double the peak power consumption due to overlapping power consumption

[0017] 5. In some special application environments, such as descrambling two different digital TV program streams at the same time, two CSA3 modules may be required to work at the same time

The present invention will provide a low-power implementation method of the CSA3 descrambling algorithm module in a DVB system, especially to solve the problem of superposition of peak power consumption that may occur when two CSA3 modules work at the same time

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