A wafer testing method

Abstract

The invention provides a wafer testing method which comprises the steps of: firstly, testing one part of crystal grains on a wafer to be tested in parallel, carrying out statistic analysis on a testing result by applying a script program so that the total yield of the wafer to be tested is judged; if the yield is better, properly reducing the testing requirement, i.e. testing residual crystal grains which are not tested by adopting a testing program for simplifying testing contents according to a product so that testing time is saved; and if the yield is poorer, keeping the original testing requirement even increasing the testing requirement, i.e. testing the residual crystal grains which are not tested by adopting the original testing program or a testing program which is stricter than the original testing program so that the accuracy of testing is ensured, wherein the testing programs are replaced automatically by depending on the script program. By adopting the wafer testing method provided by the invention, the accuracy of the testing result of the wafer can be ensured, and the testing time can be effectively saved, thus the testing cost is saved.

Description

technical field [0001] The invention relates to the technical field of semiconductor testing, in particular to a wafer testing method. Background technique [0002] The manufacturing process of semiconductor components can be roughly divided into wafer manufacturing process, wafer testing, packaging and final testing. Wafer manufacturing process is to make electronic circuit components on silicon wafers. After the manufacturing is completed, the wafers become one by one die, and then the wafer test step conducts an electrical test on the die, eliminates the unqualified die, and cuts the wafer into several dies, and packaging is to package and process the qualified die. The step of wire bonding makes the die become an integrated circuit (Integrated Circuit, IC), and finally it must go through electrical testing to ensure the quality of the integrated circuit. [0003] Please see figure 1 , figure 1 It is a schematic diagram of a wafer parallel testing method in the prior a...

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a wafer test method to solve the problem that the prior art test method cannot adjust the test strategy according to the yield rate of the wafer, thus requiring a lot of test time

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