Method for positioning fault testing vectors on basis of bisection method

Abstract

The invention discloses a method for positioning fault testing vectors on the basis of a bisection method, which comprises the following steps of: loading the testing vectors onto a circuit to be detected and outputting characteristic sequence values corresponding to the testing vectors; obtaining expected characteristic sequence values by responding to a compressor and comparing the expected characteristic sequence values with the actually measured characteristic sequence values; if the expected characteristic sequence values are inconsistent with the actually measured characteristic sequence values, obtaining a result that a certain fault points are possibly detected on the circuit to be detected, and then roughly and equally dividing a testing vector set into a first subset and a second subset; directly finding a first fault testing vector which causes the testing failure by using the first subset as a novel test object; and finishing the testing vectors which are not positioned and repeating the steps by using the testing vectors which are not positioned as a novel testing vector set until all the fault testing vectors are found. According to the positioning method disclosed by the invention, the testing vector set is divided and then the test is respectively carried out, so that the testing times are greatly reduced and the efficiency is high.

Description

technical field [0001] The invention relates to the technical field of hardware testing, in particular to the field of integrated circuit board-level production testing. Background technique [0002] With the shrinking of integrated circuit process size and the continuous improvement of circuit complexity, especially the emergence and wide application of System-on-Chip (SoC), the integration level of VLSI has been developed to the point where one chip can Integrate more than tens of millions of transistors. Therefore, exploring and applying low-cost, high-efficiency testing techniques and testing systems has become an important topic in chip testing. [0003] When logic built-in self-test technology (Logic Built-In Self-Test, LBIST) is used for chip-level fault testing, the fault coverage and fault location accuracy of the test depend on the diagnostic capability of the test vector, and the test time depends on the logic built-in self-test (LBIST). The number of self-tests...

AI Technical Summary

Problems solved by technology

Please refer to figure 1 As shown, the traditional linear positioning method needs to perform a single test for each test vector in the test vector set to finally confirm all the test vector combinations that cause the test failure. This method has the disadvantages of long test time and many test times. question

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