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Delay latch circuit and delay flip-flop

A latch circuit, delay time technology, applied in static memory, read-only memory, digital memory information and other directions, can solve problems such as circuit failure

Inactive Publication Date: 2012-08-01
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The resulting contention thus prevents the inverter loop from maintaining its correct information, causing the circuit to malfunction

Method used

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  • Delay latch circuit and delay flip-flop
  • Delay latch circuit and delay flip-flop
  • Delay latch circuit and delay flip-flop

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0047] [Structure of sequential circuit]

[0048] figure 1is a circuit diagram showing a typical structure of the sequential circuit 100 as the first embodiment of the present disclosure. The sequential circuit 100 is composed of inverters 110 and 120 and a D flip-flop 130 . The D flip-flop 130 includes a master D-latch circuit 210 , a slave D-latch circuit 220 , and inverters 230 and 240 . The data signal D and the clock signal CK are input to the sequential circuit 100 .

[0049] The data signal D is a signal representing one bit of information. The data signal D is input to the D latch circuit 210 via the signal line 901 . The clock signal CK is a signal that controls the operation of the D flip-flop 130 . The D flip-flop 130 samples data at a timing of a rising edge of a clock signal, and holds data at other timings.

[0050] The inverter 110 inverts the clock signal CK. The inverter 110 thus inverts the clock signal CK into an inverted clock signal CKB, and outputs...

no. 2 example

[0139] [Structure of sequential circuit]

[0140] Figure 14 is a circuit diagram showing a typical structure of the sequential circuit 101 as the second embodiment of the present disclosure. The structure of the sequential circuit 101 is basically the same as that of the sequential circuit 100 of the first embodiment except that a D flip-flop 131 replaces the D flip-flop 130 . The D flip-flop 131 is composed of a master D latch circuit 211 , a slave D latch circuit 221 and an inverter 240 .

[0141] The D latch circuit 211 holds data or becomes transparent to data according to a clock signal CK. Specifically, the D latch circuit 211 performs predetermined logic operations with respect to the inverted clock signal CKB and the data signal D. Referring to FIG. Logical operations will be discussed in detail later. If the clock signal CK is high as a result of the logic operation, the D latch circuit 211 holds the inverted signal of the data signal D as the inverted output sig...

no. 3 example

[0156] [Structure of sequential circuit]

[0157] Figure 17 is a circuit diagram showing a typical structure of the sequential circuit 102 as the third embodiment of the present disclosure. The structure of the sequential circuit 102 is basically the same as that of the sequential circuit 100 of the first embodiment except that a D flip-flop 132 replaces the D flip-flop 130 . The D flip-flop 132 is composed of a master D-latch circuit 212 , a slave D-latch circuit 222 and an inverter 240 .

[0158] The D latch circuit 212 holds data or becomes transparent to data according to the clock signal CK2. Specifically, the D latch circuit 212 performs predetermined logic operations with respect to the clock signal CK2 and the data signal D. Referring to FIG. Logical operations will be discussed in detail later. If the clock signal CK is low as a result of the logic operation, the D latch circuit 212 holds the inverted signal of the data signal D as the inverted output signal QMB ...

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PUM

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Abstract

Disclosed herein are a delay latch circuit and a delay flip-flop circuit arranged to inhibit the increase in power consumption while preventing malfunction under low voltage conditions. An internal signal output circuit outputs as an internal signal an inverted signal of a data signal starting from an internal transparency start timing until an internal transparency end timing. From the internal transparency end timing until the internal transparency start timing, the internal signal output circuit outputs a fixed value signal as the internal signal. A transistor delays the output internal signal over a time period which ranges from a hold instruction delay timing to the issuance of a data transparency instruction and which includes the internal transparency end timing therebetween.

Description

technical field [0001] The present disclosure relates to delay latch circuits and delay flip-flops. More specifically, the present disclosure relates to delay latch circuits and delay flip-flops that can be used under low voltage conditions. Background technique [0002] So far, sequential circuits have used D (delay) latch circuits and D flip-flops as circuits for holding states, respectively. These D latch circuits and D flip-flops may employ wired OR (logic addition) circuits. A wired-OR circuit is a circuit that provides OR logic by connecting multiple outputs in parallel. For example, consider a D latch circuit or a D flip-flop circuit that uses an inverter loop to hold bit information. A wired-OR circuit is formed when the two inverters making up the inverter loop are wired in parallel to the appropriate gate terminals that input data to the inverter loop. Although circuits have tended in recent years to require operation at low voltages, it is well known that at l...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/06G11C16/10
CPCH03K3/35625H03K3/037H03K3/0375G11C19/00
Inventor 平入孝二
Owner SONY CORP