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Random excitation flash model verification method

A technology of model verification and random excitation, which is applied in static memory, instruments, etc., can solve the problems of inflexible constraint block programming and inflexible excitation generator, and achieve the effects of shortening the development cycle, reducing occupation, and simple syntax

Inactive Publication Date: 2012-08-01
SHANDONG SINOCHIP SEMICON
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Problems solved by technology

System Verlog emphasizes the use of reusable verification IP (Intellectual Property) in verification, including how to generate randomized stimuli, but the use of simple instantiated stimuli generators is not flexible enough. One of the main problems is how to add New constraint blocks; this creates a contradiction between the flexibility requirements of randomized incentives and the inflexibility of constraint block programming

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  • Random excitation flash model verification method
  • Random excitation flash model verification method

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Embodiment Construction

[0026] Refer to the attached figure 1 , a random excitation flash memory model verification method, writes a pseudo-assembly command weight script according to the weight of non-flash memory operation commands, saves it in a disk file, and uses the file read and write method;

[0027] According to the non-flash model reading and non-flash parameters and test conditions, configuration and non-flash model interface driver;

[0028] Calling the pseudo-assembly command weight script randomly generates assembly pseudo-commands, and generates a pseudo-assembly test sequence by taking the command weight as a constraint condition to generate a predetermined total number of compilation pseudo-commands;

[0029] The pseudo assembly test sequence is analyzed, and the flash memory model is tested through the interface driver.

[0030] Pseudo-assembly is included in the assembly language of computer communication majors, and it is also involved in other disciplines involving computer / micr...

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Abstract

The present invention discloses a random excitation flash model verification method. The method comprises: writing a pseudo-assembler command weight script according to a nandflash operation command weight; reading parameters and testing conditions of a nandflash according to the nandflash model, and configuring interface driving of the nandflash model; calling the pseudo-assembler command weight script to randomly generate a assembler pseudo-command, and adopting the command weight as the constraint condition to produce a predetermined total number of assembler pseudo-commands so as to generate a pseudo-assembler test sequence; parsing the pseudo-assembler test sequence, and performing a test on a flash model through the interface driving. With the verification method of the present invention, high test coverage can be provided for different flash models.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, packaging and testing, and in particular relates to a flash memory model verification method. Background technique [0002] Nandflash (and non-flash memory) is a very popular storage medium in the industry at present. It has the advantages of small storage unit area, fast programming speed, and short erasing time. Therefore, Nandflash is used in almost all erasable memory cards. [0003] In the commonly used digital SOC (system on chip, system on chip) chip architecture, the Nandflash controller is often used to communicate with the Nandflash flash memory device outside the chip. As a bridge between the processor in the SOC chip and the Nandflash flash memory, the flash memory controller implements operations such as programming and erasing the Nandflash by issuing instructions to the flash memory. Therefore, the Nandflash controller plays an irreplaceable role in the communica...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/56
Inventor 刘松陆崇心李峰张洪柳
Owner SHANDONG SINOCHIP SEMICON
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