Chemical mechanical lapping method

A grinding method and chemical mechanical technology, which is applied in the field of semiconductor technology, can solve the problems of insufficient cleaning effect, insignificant effect, and no better solution, etc., and achieve the effect of removing organic residues

Active Publication Date: 2012-08-01
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, after using the cleaning method to clean the wafer, it is found that the number of some larger pollutant particles is still large, and this method is not effective in removing organic residues on the surface of the wafer, and the expected cleaning effect cannot be achieved.
[0005] Therefore, in view of the above problems, it is necessary to provide a method that can effectively remove organic residues on the wafer surface, but there is no better solution at present

Method used

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Embodiment 1

[0037] Embodiment 1: Reference Figure 2 to Figure 4 Schematic diagram of chemical mechanical polishing during formation of dual damascene structures shown.

[0038] Specifically, refer to figure 2 As shown, first, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 contains a metal wiring layer ( figure 2 not shown in); forming a cover layer 101 on the semiconductor substrate 100, the cover layer 101 covering the metal wiring layer; and forming a dielectric layer 102 on the cover layer 101 by a chemical vapor deposition (CVD) method, the medium The material of layer 102 is silicon dioxide, low-K (dielectric constant) material, and the like.

[0039] In this embodiment, the covering layer 101 can prevent the metal wiring in the semiconductor substrate 100 from diffusing into the dielectric layer 102, and can also prevent the metal wiring in the semiconductor substrate 100 from being etched during the etching process.

[0040] continue to refer ...

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Abstract

The invention provides a chemical mechanical lapping method which comprises the following steps of: providing a semiconductor substrate formed with a dielectric layer; carrying out a first time of lapping to the dielectric layer, wherein organism residue is generated on the surface of the dielectric layer after the first time of lapping; carrying out a second time of lapping to the dielectric layer by adopting an alkaline reagent to remove the organism residue on the surface of the dielectric layer. According to the invention, the alkaline reagent is adopted to remove the organism residue on the surface of the dielectric layer after main lapping process is completed to a wafer and before cleaning of the wafer by adopting the subsequent process in the existing chemical mechanical lapping process; and compared with the prior art, the chemical mechanical lapping method provided by the invention has the advantages that the effect for removing the organism residue is more obvious, thereby improving the quality and performance of final products.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a chemical mechanical polishing method. Background technique [0002] In the field of semiconductor technology, chemical mechanical polishing technology (CMP technology) has both mechanical polishing and chemical polishing, which can flatten the entire wafer surface for subsequent thin film deposition and other processes. During the CMP process, the wafer to be ground is pressed against the grinding pad by the grinding head and the wafer is driven to rotate, while the grinding pad rotates in the opposite direction. When grinding, the required grinding slurry is added between the wafer and the grinding pad through the grinding slurry delivery device; then, with the high-speed direction between the grinding pad and the wafer to be ground, the wafer to be ground The reaction products on the surface are continuously peeled off, and the reaction products are carried away with ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/3105H01L21/02B24B37/04
CPCH01L21/3212H01L21/31053H01L21/7684H01L21/76819H01L21/02074
Inventor 邓武锋
Owner SEMICON MFG INT (SHANGHAI) CORP
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