Router device suitable for globally asynchronous locally synchronous on-chip network

Abstract

The invention discloses a router device suitable for globally asynchronous locally synchronous on-chip network. The router device is provided with three pipeline levels and is characterized in that the conversion of caching and clock domain is carried out on a microchip at a BW / RC level, by using the delay of clock domain conversion, the routing computation is carried out on data packets, and computation results are synchronized; the right of use of a virtual channel and a crossbar switch are applied for in a speculation manner at a VA / SA level, a virtual channel distributor arbitrates the request of the virtual channel, a crossbar switch distributor only arbitrates the request of the crossbar request of a non-speculation chip, an arbitration result which the virtual channel asks for is directly used as the arbitration result of a microchip speculation application crossbar switch, and the crossbar switch distributor preferentially selects the arbitration result which a non-speculation crossbar switch asks for as the final distribution result of the crossbar switch; and a crossbar switch selector is communicated with the corresponding virtual channel from an input port to an output port according to the arbitration result of the crossbar switch at a ST level, and the microchip departs from asynchronous buffering and passes the router.

Description

technical field [0001] The invention relates to a router device suitable for a global asynchronous local synchronous on-chip interconnection network. Background technique [0002] With the continuous advancement of integrated circuit technology, more and more intellectual property cores can be integrated on a single chip, and the system's demand for communication bandwidth is also increasing. In traditional chips, the bus is usually used as the main structure for communication between various devices. However, a bus can only support communication between a pair of devices at the same time, and the bus bandwidth will not increase with the number of bus devices. With problems such as delay and increased power consumption, it has been unable to meet the communication requirements between intellectual property cores. Therefore, researchers draw on the parallel computer interconnection network technology and propose that the on-chip interconnection network is used to replace the...

AI Technical Summary

Problems solved by technology

2) Forward-looking routing requires expanding the bit width of each item in the virtual channel cache to store routing calculation results, which increases the cost of the cache

A data packet has only one header flake, and the utilization rate of the extension bit of the routing calculation result is very low

3) Forward-looking routing cannot reduce the demand for the number of routing computing units

Since none of the microchips can obtain the right to use the virtual channel and the crossbar at the same time, neither microchip can leave the current router in the next clock cycle, and the purpose of speculation has not been achieved.

In the case of simultaneous speculation of multiple data packets, the speculative success rate of the document 1 scheme cannot reach 100%, because the design of document 1 cannot guarantee that the licenses for virtual channel allocation and speculative crossbar allocation are all granted to the same microchip

[0021] The crossbar allocator in Document 1 needs to use two arbitrators to arbitrate the non-speculative crossbar request and the speculative crossbar request respectively, while in the crossbar allocator of a common 5-level pipeline router, only one arbitration is required tors, with increased circuit overhead than between

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