Solid-state storage system with parallel access of multiple flash/PCM devices

Abstract

Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random / burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random / burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional / operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I / O performance in terms of maximum achievable read / write data rate.

Description

Background technique

[0001] Currently, flash-based storage is the most common non-volatile RAM technology in solid-stat drives (SSDs), but it is foreseeable that in the near future, phase-change storage-class memory (phase-change storage-class memory, PCM) other technologies will be used in solid-state storage systems. A common way to achieve high-performance I / O is to use multiple independent channels that are accessed in parallel. The data rate achieved in each channel is primarily limited by the "Page Write" and "Page Read" times required internally by the flash device to complete the respective operations, and the clock rate at the device interface .

[0002] Currently in SSDs, besides cost and I / O performance, one of the major issues with using flash chips or flash integrated circuit devices (ICs) is reliability and endurance issues due to the amount of write / erase that can be performed in the flash cells due to the limited number of division operations. This phenomen...

Images