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Air gap technology applied to copper interconnection

A technology of air gap and copper interconnection, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of residues and difficult removal of metals, and achieve the effect of solving metal residues and ensuring integrity

Active Publication Date: 2017-04-19
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The invention provides an Air-Gap process applied to copper interconnection, which solves the problem of metal residue caused by difficult metal removal in the process, and has the characteristics of simple implementation and compatibility with existing CMOS processes.

Method used

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  • Air gap technology applied to copper interconnection
  • Air gap technology applied to copper interconnection
  • Air gap technology applied to copper interconnection

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Experimental program
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Embodiment 1

[0040] Please refer to Figure 1A~1IIn this embodiment, the trench and the metal copper filling process are completed by the single damascene process of copper damascene, and then the Air Gap is formed by the process of releasing the sacrificial layer and depositing the dielectric layer. This embodiment can be used to implement Air Gap in Pre-Metal Dielectric (PMD, Pre-Metal Dielectric), and can also be used to implement Air Gap of IMD or ILD when a metal layer or through hole is fabricated by a single damascene process.

[0041] Please refer to Figure 1A , First, a substrate 101 is provided, the substrate 101 is a silicon substrate, the substrate 101 has completed the previous process, and a metal interconnection layer 102 is formed in the substrate 101. The device 103 to be leaded is used for subsequent metal interconnection. The device to be leaded 103 in this embodiment is a metal silicide or a front-layer metal.

[0042] Please refer to Figure 1B , a sacrificial layer...

Embodiment 2

[0064] The difference from the first embodiment is that in this embodiment, the trenches are formed by the copper damascene process and filled with metal, and then the sacrificial layer is released and the dielectric layer is deposited to form the Air Gap. This embodiment can be used for the realization of Air Gap in the double damascene process, which is combined below Figure 2A ~2L describes this embodiment in detail.

[0065] Please refer to Figure 2A , First, a substrate 201 is provided, a metal interconnection layer 202 is formed in the substrate 201, a device to be lead 203 is arranged between the metal interconnection layers 202, and a sacrificial layer 204 is formed on the surface of the substrate; patterning The sacrificial layer 204 on the to-be-leaded device 202 forms a pattern 205 with a large top and a small bottom. The above steps in this embodiment use the same process conditions as those in the first embodiment, which will not be repeated here.

[0066] Ple...

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Abstract

The invention discloses an air-gap process applied to copper interaction, comprising the following steps of: imaging a sacrificial layer to form a graph with big top and small bottom, and filling a first dielectric layer in the graph; forming a groove or a groove and through hole structure in the first dielectric layer, filling metallic copper and carrying out planarization; removing the sacrificial layer; and depositing a second dielectric layer on a substrate, the first dielectric layer and the metallic copper, thus an air gap is formed. The graph with the big top and the small bottom is formed, thus a releasing opening is formed between the top of the sacrificial layer and the first dielectric layer, the air gap can be easily formed by virtue of deposition on the second dielectric layer after the sacrificial layer is removed, and completeness of sealing on the air gap in a subsequent process is ensured; besides, metal is firstly filled into the groove, then the second dielectric layer is deposited on the substrate, and the air space is formed, thus metal residue problem caused by the fact that the metal is accumulated in an open region of a line and is difficultly removed can be solved.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to an air spacer process applied to copper interconnection. Background technique [0002] Integrated Circuits (ICs) continue to shrink in accordance with Moore's Law, and the integration level is getting higher and higher. At the same time, higher and higher requirements are placed on various performances of devices. Among them, the back end process (BEOL, Back EndofLine) introduces Resistor-capacitor delay (RC Delay) has become an increasingly important factor that cannot be ignored. The resistance-capacitance time delay (τ) is proportional to the resistance of the metal connection and the parasitic capacitance between the fill dielectric and the metal: [0003] τ∝RC int tot =R(C IMD +C ILD ) Formula 1) [0004] In formula (1), R is the resistance of the metal connection, C IMD and C ILD They are the capacitance between metal connections and the capacitance be...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 袁超康晓旭
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT