Field effect transistor
A technology of field-effect transistors and transistors, which is applied in the fields of electrical solid-state devices, semiconductor devices, semiconductor/solid-state device manufacturing, etc., and can solve problems such as cost increase, device layout that cannot be used as it is, and area increase.
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no. 1 example
[0036] exist figure 1 (a) and figure 1 A field effect transistor (hereinafter also referred to as a transistor) according to the first embodiment is shown in (b). figure 1 (a) is a cross-sectional view of the transistor of the first embodiment. figure 1 (b) is by figure 1 (a) An enlarged view of the area 20 enclosed by the dotted line shown. The transistor of the first embodiment is formed on a semiconductor substrate including a semiconductor layer 2 , an insulating film 4 formed on the semiconductor layer 2 , and a semiconductor layer 6 formed on the insulating film 4 . For example, a Si layer is used as the semiconductor layer 2 . Use Si 1-x Ge x The (0≤x≤1) layer serves as the semiconductor layer 6 . In the case where the semiconductor layer 6 is not a Si layer or the semiconductor layer 6 contains Ge, the semiconductor layer 6 preferably has strain. In the following description, the semiconductor layer 6 is a Ge layer. A gate insulating film 8 is formed on the Ge...
no. 2 example
[0048] now refer to Figure 5 (a) and Figure 5 (b), describing the transistor according to the second embodiment. Figure 5 (a) is a cross-sectional view of a transistor according to the second embodiment. Figure 5 (b) is a graph showing I-V characteristics of the transistor according to the second embodiment.
[0049] Except that each of the source region and the drain region is made of an intermetallic compound, the transistor of the second embodiment is the same as figure 1 The transistors of the first embodiment shown in (a) are the same. That is, the source region and the drain region are source region 17 a and drain region 17 b made of metal (intermetallic compound), and are designed to have a Schottky junction with semiconductor layer 6 . By forming such a metal source / drain structure, carriers are injected from the metal source region 17a into the channel region. Through the structure, such as Figure 5 As shown in (b), the S value exceeding the limit value of ...
no. 3 example
[0057] Figure 9A transistor according to the third embodiment is shown. In addition to providing an extension region 19a formed by introducing a dopant on the side of the source region 17a, setting a side wall 12 made of a high dielectric material as a side wall on the drain side, and setting a side wall made of a low dielectric material (for example, SiO 2 The transistor of the third embodiment is the same as the transistor of the second embodiment except that the side wall 13 made of SiN) is used as the side wall on the source side. This structure can also be applied to figure 1 The first embodiment shown. That is, in the transistor having the source region 14a and the drain region 14b formed between the semiconductor layer 6 and the source electrode 18a and the drain electrode 18b by introducing a dopant as in the present embodiment, the source region 14a side is provided with an extension region formed by introducing dopants, the sidewall on the drain side can be made...
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