Parallel cyclic redundancy check method and device in high-speed Ethernet
A cyclic redundancy check, Ethernet technology, applied in the field of communication and computer data transmission error control, can solve problems such as narrow use range and multiple logic resources, and achieve the effect of wide application range, reduced logic resources, and high frequency
Active Publication Date: 2012-10-24
UTSTARCOM TELECOM CO LTD
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[0006] The purpose of the present invention is to provide a parallel cyclic redundancy check method and device to solve the problems of occupying more logic resources and narrow application range in the prior art
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[0034] In order to make the technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. .
[0035] In this embodiment, the present invention will be described in detail by taking the operating bandwidth of data as 64 bits and using a 64-bit CRC32 check module as an example. Such as figure 1 As shown, the parallel CRC checking method of the present invention comprises steps:
[0036] Step 101, performing bit width matching on the data frame with a 64-bit bit width, to determine the number of effective data bits in the last beat;
[0037] Step 102, sending the data frame into a general 64-bit cyclic redundancy check CRC32 module for calculation to obtain a check value, and the processing range is from the frame header to the frame t...
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The invention discloses a parallel cyclic redundancy check method in a high-speed Ethernet, which is used in a cyclic redundancy check (CRC) module to carry out parallel cyclic redundancy check. The parallel cyclic redundancy check method comprises the following steps of: at first, carrying out bit width matching on data frames according to a pre-set bit width; then sending matched data flow to the universal bit width pre-setting parallel cyclic redundancy check module and calculating a check value; and finally, carrying out inverse operation on the check value obtained through the calculation according to the last effective data bit, so as to obtain a final CRC result. The invention further discloses a parallel cyclic redundancy check device, comprising the CRC module for pre-setting the bit width, a register and a last data inverse operation module. The device provided by the invention has a simple structure. With the adoption of the CRC module with the certain bit width, the high-speed parallel data CRC can be realized. Furthermore, the method provided by the invention is applicable to the high-speed parallel data CRC with the random bit width and has a wide application range.
Description
technical field [0001] The invention relates to the technical field of communication and computer data transmission error control, in particular to a parallel cyclic redundancy check calculation method in high-speed Ethernet communication. Background technique [0002] In data communication, data packets are generally transmitted, followed by a frame check sequence (FCS, Frame Check Sequence) for error control coding to ensure the correctness of transmission. In the realization of the frame check sequence, the Cyclic Redundancy Code (CRC) has been widely used for its high efficiency and high performance. It is a method commonly used in the current data transmission process to improve the reliability of data communication. . [0003] In real-time high-speed communication systems, the traditional bit-based serial CRC generation and verification circuits have long been unable to meet the requirements of high-speed and parallel information processing. Parallel CRC check must b...
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IPC IPC(8): H04L1/00H04L12/56
Inventor 梁凯平王兆明
Owner UTSTARCOM TELECOM CO LTD