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Latch circuit and display device using the latch circuit

A latching circuit and latching control technology, applied in electrical components, static indicators, generating electrical pulses, etc., can solve the problems of heavy manufacturing process burden, and achieve the effect of reducing the burden

Inactive Publication Date: 2015-10-14
SNAPTRACK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0020] However, the CMOS manufacturing process using a MOS transistor whose semiconductor layer is made of polysilicon generally requires about 6 to 10 photolithography steps, so it can be said that the burden on the manufacturing process of the structure of the latch circuit formed by the conventional CMOS circuit Big

Method used

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  • Latch circuit and display device using the latch circuit
  • Latch circuit and display device using the latch circuit
  • Latch circuit and display device using the latch circuit

Examples

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Comparison scheme
Effect test

Embodiment 1

[0049] figure 1 is a circuit diagram showing a circuit configuration of a single-channel latch circuit (hereinafter, simply referred to as a latch circuit) according to Embodiment 1 of the present invention. The latch circuit of this embodiment is a single-channel MOS transistor circuit composed of only n-type MOS transistors (NMT*) (hereinafter, simply referred to as transistors). In addition, the n-type MOS transistor (NMT*) of this embodiment is a thin film transistor (hereinafter referred to as an a-Si transistor) whose semiconductor layer is made of amorphous silicon.

[0050] In addition, in figure 1 Among them, CD1 and CD2 are capacitors, LD is a data line, LG is a scanning line, LAC1 is the first latch control line supplied with the first drive clock (φAC1), and LAC2 is the first latch control line supplied with the second drive clock (φAC2). Two latch control lines, LAC3 is a third latch control line supplied with a third drive clock (φAC3).

[0051] In a circuit...

Embodiment 2

[0110] Figure 4 It is a circuit diagram showing a circuit configuration of a single-channel latch circuit according to Embodiment 2 of the present invention.

[0111] Figure 4 The latch circuit shown is in the figure 1 In the latch circuit shown, the capacitor (CD2) and the transistor (NMT5) are deleted, and the node (N3) is used as the first output (OUT1).

[0112] Figure 5 express Figure 4 The scanning voltage (φG), the first to third driving clocks (φAC1 to φAC3) and the time changes of each node (N1, N2, N3) of the latch circuit are shown.

[0113] At time (t1), when the scanning voltage (φG) on the scanning line (LG) changes from the L-level VL voltage to the H-level VH1 voltage, the input transistor (NMT1) is turned on, and the voltage of the node (N1) It becomes the voltage on the data line (LD) (data is VL voltage at time (t1)).

[0114] At time (t2), when the scanning voltage (φG) on the scanning line (LG) changes to the L-level VL voltage, the transistor (...

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Abstract

A single channel latch circuit is provided which can latch data in a comparatively short period of time and can achieve low costs. The latch circuit includes an input transistor (NMT1), a retention capacitor (CD1) connected between a second electrode of the input transistor (NMT1) and a first latch control line (LAC1), a first transistor (NMT2) in which a first electrode is connected to the first latch control line (LAC1) and a gate is connected to the second electrode of the input transistor (NMT1), a second transistor (NMT4) in which a gate is connected to the second electrode of the first transistor (NMT2) and a first electrode is connected to the second latch control line (LAC2), a third transistor (NMT5) in which a gate is connected to the second electrode of the first transistor (NMT2) and a first electrode is connected to the second electrode of the second transistor (NMT4) and a second electrode is connected to an output terminal (OUT1), a capacitor (CD2) connected between the second electrode of the first transistor (NMT2) and the second electrode of the second transistor (NMT4), and a diode (NMT3) connected between the second electrode of the first transistor (NMT2) and the first latch control line (LAC1).

Description

[0001] This application claims priority based on Japanese Patent Application No. 2011-106895 filed on May 12, 2011, the entire contents of which are incorporated herein by reference. technical field [0002] The present invention relates to a latch circuit (latch circuit) and a display device using a latch circuit, in particular to a single-channel latch circuit that uses only any one of n-type MOS transistors and p-type MOS transistors to form a latch circuit and its use. A display device with a single-channel latch circuit. Background technique [0003] Generally speaking, a latch circuit is usually composed of a CMOS circuit, and a common latch circuit such as Figure 8 As shown, n-type MOS transistors (NMT93, NMT94) and p-type MOS transistors ( PMT95, PMT96). [0004] Figure 9 express Figure 8 The scanning voltage (φG), the drive clock (φAC) and the time variation of each node (N91, N92, N93, N94) are shown. [0005] First, a case where the voltage (data) on the dat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/037G09G3/00
CPCH03K3/356095G09G3/20H03K3/356
Inventor 宫泽敏夫宫本光秀
Owner SNAPTRACK