Optical on-chip network system of non-blocking communication and communication method thereof

Abstract

The invention discloses an optical on-chip network system of non-blocking communication and a communication method thereof and mainly solves the blocking problem of the existing optical on-chip network system. The optical on-chip network system comprises a light transmission network and an electric control network; each node in the light transmission network comprises an IP (Internet Protocol) core, a sending unit, a receiving unit and a light exchanging device, wherein the sending length of each sending unit is fixed and the light exchanging device is formed by light vertical switches; and the inner structures of all the receiving units are the same. The communication method comprises the following steps of: firstly, establishing a two-dimensional coordinate system for the light transmission network and reading coordinates of a source node and a target node; secondly, opening a needed micro-ring resonator by the electric control network according to the source node and the target node; and finally, transmitting the light information to the target node by the light transmission network to be processed, and closing the opened micro-ring resonator. The optical on-chip network system disclosed by the invention combines a wavelength division multiplexing technology, a space division multiplexing technology and a light circuit exchanging technology to realize the non-blocking communication of the IP cores and improve the resource utilization rate and the throughput performance of the network.

Description

technical field [0001] The invention belongs to the technical field of communication, in particular to an optical on-chip network system for non-blocking communication, which supports non-blocking communication between on-chip processors, improves network resource utilization and delay throughput performance, and supports many-to-one non-blocking communication . Background technique [0002] The system-on-chip based on the bus structure is to integrate multiple IP cores on the chip through the bus interconnection. In the process of developing towards multi-core and heterogeneity, the system-on-chip has low communication efficiency due to the bus structure. Problems such as poor scalability have gradually become the bottleneck limiting the performance of on-chip communication. Therefore, the network on a chip came into being. The core idea of ​​the network on chip is to transplant the computer network technology into the chip design, so as to completely solve the problems c...

AI Technical Summary

Problems solved by technology

Too many waveguides also increases chip area and layout complexity

[0006] Although the above two methods can reduce the probability of blocking, they cannot truly achieve non-blocking communication; at the same time, the resource utilization rate of these two methods is low, and the throughput performance is poor.

Images