Manpower cost management method for large-scale integrated circuit testing

Abstract

The invention belongs to the electronic design automation field of large-scale integrated circuit design verification, and particularly relates to a manpower cost management method for the large-scale integrated circuit testing. According to the method, as the condition of the contradictory problem between the restricted manpower cost and an operation of pursuing the acute maximal functional coverage rate index in a testing process, and the problem that how to distribute quantitative indexes (improved in each test) by managers are solved, the optimum utilization of the manpower cost can be achieved is realized, and the functional coverage rate of testing can be quickly up to the maximum value. According to the method, the functional coverage rate and the disk dosage are set as a power function of time in an information modeling mode, and based on a geometric programming method, the optimal solution gamma* of the maximal functional coverage rate and the sensitivity of gamma* to the constraint that Beta i (i = 1, 2,..., N) is greater than or equal to Beta i gamma*0 and is less than or equal to 1 is obtained, wherein the N refers to the number of regression testing; then, the manpower cost of each test is set as a power function of improved quantitative indexes in a modeling mode; and finally, the optimal manpower resource management problem is transformed into a geometric programming problem, thereby obtaining the optimal quantitative index required to be improved in each test and the optimal value of the maximal functional coverage rate after the improvement.

Description

technical background [0001] The invention belongs to the electronic design automation (EDA) field of large scale integrated circuit (VLSI) design verification, in particular to a human cost management method for large scale integrated circuit testing. Background technique [0002] The verification work of VLSI design is of great significance to ensure the correctness of the function of the chip. In the design process of VLSI, the regression test runs throughout. VLSI design is generally described in RTL code. When the RTL code is slightly modified, all existing tests must be run repeatedly to ensure that the modification does not introduce design errors. For complex VLSI designs with multiple RTL modules, multiple verification personnel participate in the writing of regression tests, and there are many regression tests. In order to quickly achieve the overall 100% functional coverage index, testers are required to perform multiple tests for each test Improvement, of course,...

AI Technical Summary

Problems solved by technology

For complex VLSI designs with multiple RTL modules, multiple verification personnel participate in the writing of regression tests, and there are many regression tests. In order to quickly achieve the overall 100% functional coverage index, testers are required to perform multiple tests for each test Improvement, of course, the improvement of each test needs to invest in labor costs, and the actual labor costs are limited, and it is impossible to have unlimited

Therefore, there is the following problem: In a certain state, how does the manager determine which test to improve first, and to what extent, so that the overall functional cov

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