Stress sensor transfer method used for measuring wafer level packaging stress

Abstract

The invention relates to a stress sensor transfer method used for measuring the wafer level packaging stress, which comprises the following steps of: manufacturing a stress sensor on top layer silicon of an SOI (Silicon-On-Insulator) silicon wafer; attaching the stress sensor to a test wafer with the same size to a wafer to be packaged to the stress sensor in a face-to-face way by using an organic glue film; and removing substrate silicon of the stress sensor through etching, and transferring a chip unit of the stress sensor to the test wafer. In the invention, the stress sensor is manufactured on a small-size silicon wafer, the processing cost of the small-size silicon wafer is obviously lower than that of a large-size silicon wafer, a chip cut from one sensor wafer can meet the use level of a plurality of test wafers, and the use cost is far lower than that of directly manufactured large-size test wafers.

Description

technical field [0001] The invention relates to the technical fields of integrated circuit manufacturing, packaging and measurement, in particular to a stress sensor transfer method for wafer-level packaging stress measurement. Background technique [0002] The packaging process of the integrated circuit introduces stress in the integrated circuit chip. Since the carrier mobility of semiconductor materials such as silicon will change with stress, packaging stress will have a significant impact on the performance of integrated circuits. In addition, material fatigue caused by package stress changing with temperature is an important cause of integrated circuit failure. It is generally necessary to reduce packaging stress through optimization of materials, packaging structures, and processes. [0003] The stress sensor fabricated by utilizing the piezoresistive effect of silicon is a powerful tool for package stress measurement. The piezoresistive stress sensor uses the piez...

AI Technical Summary

Problems solved by technology

The processing cost of 8-inch or 12-inch integrated circuit process line is high, and the development cost is high due to the small amount of test wafers

High development costs limit the application of stress sensors in wafer-level packaging

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