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Full spectrum modulator for digital television signals

一种调制器、全频谱的技术，应用在彩色电视的零部件、电视系统的零部件、电视等方向，能够解决不能满足5ppm频率精度规格等问题

Inactive Publication Date: 2012-12-26
RGB NETWORKS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] 2. It cannot meet the 5ppm frequency accuracy specification
[0013] 4. The polyphase resampler requires 720x47 real multipliers, which overly constrains resources and layout for any potential FPGA implementation

Method used

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  • Full spectrum modulator for digital television signals
  • Full spectrum modulator for digital television signals
  • Full spectrum modulator for digital television signals

Examples

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Embodiment Construction

[0032] The first embodiment of the present invention is in Figure 4 In the description, Figure 4 is a block diagram of a full spectrum downstream TV modulator that can fit within a single FPGA or ASIC and can utilize a single D / A converter. exist Figure 4 Proceeding from left to right in , complex QAM symbols are injected as input from a symbol mapper (not shown) into a square-root self-multiplied cosine filter (SRRC) and a 1:2 interpolator 40, which simultaneously passes through two upsampled channel frequency (eg, from 5.36MHz to 10.72MHz) and pulse-shape the signal. There are potentially 158 independent QAM channels which together form the entire 1 GHz DOCSIS / CATV downstream signal. Each of these lanes may be composed of respective components corresponding to components 40, 42, 44, 46, and 48 described in detail herein (e.g., SRRC 1:2 interpolator 40′, Phino cubic interpolator 42′, The mixer 44', the direct digital synthesizer 46' and the decimator 48') are processed in...

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Abstract

The invention relates to a full spectrum modulator for digital television signals. The full spectrum modulator processes a plurality of CATV channels from separate paths. Each path has (i) a first filter for pulse shaping an input channel signal and upsampling a channel frequency thereof, (ii) an interpolator for interpolating the output of the first filter to a common sample rate, and (iii) a decimator for centering the output of the interpolator on a predetermined channel bandwidth. An IDFT processor receives channel signal outputs from the decimators. A polyphase filter bank receives IDFT processed parallel channel signals from the IDFT processor. A commutator converts the processed parallel channel signals from the polyphase filter bank to a single stream of data. A second filter upsamples the single stream of data to a fixed output sampling rate and low pass filters alias signals therefrom. Both standard and harmonically related carrier CATV channel frequency plans are accommodated.

Description

technical field [0001] The present invention relates to the communication of digital television signals and / or digital data signals (eg, DOCSIS - Data Over Cable Service Interface Specification) over a cable television (CATV) distribution system or the like. More specifically, the present invention provides a digital signal processor (DSP) implementation of a full-spectrum downstream modulator (which is DOCSIS compliant) that fits on a single FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) ) and can be implemented using a single digital / analog (D / A) converter. Background technique [0002] In recent years, the number of quadrature amplitude modulation (QAM) channels used for narrowcast digital television services has increased substantially. Most multiple system operators (MSOs) are providing more and more unicast QAM channels to support the growth brought about by the success of video-on-demand (VOD) services. This has been driven in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L27/36H04N5/40
CPCH04H20/77H04L27/36H03C5/00H04H20/78
Inventor 凯南·劳德尔
Owner RGB NETWORKS
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