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Non-through-hole connected copper mutual connection method

A non-through-hole, copper interconnection technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., to avoid negative effects, achieve line width, and achieve the effect of no etching process

Active Publication Date: 2013-02-27
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] It can be seen that the non-planarization characteristics of the mosaic structure in the existing copper interconnection process has caused a certain negative impact on the process, and has become one of the technical problems to be solved by those skilled in the art

Method used

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  • Non-through-hole connected copper mutual connection method

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Embodiment Construction

[0028] Please also see Figure 1a to Figure 1f , are schematic diagrams of process steps of the first embodiment of the copper interconnection method for non-through-hole connection of the present invention, and the method of this embodiment includes the following steps:

[0029] Step S01, providing a substrate, forming a lower copper metal layer on the substrate according to a standard process, the lower copper metal layer includes a first lower copper metal 11 that needs to be connected to the upper copper metal layer and a first lower copper metal layer that does not need to be connected to the upper copper metal layer The second lower layer of copper metal 12, and deposit a layer of silicon nitride through-hole mask layer 2 on the formed lower layer of copper metal layer, wherein the thickness of the lower layer of copper metal layer is 200nm, such as Figure 1a shown;

[0030] Step S02, performing photolithography through a non-through-hole photolithography plate, the pho...

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Abstract

The invention discloses a non-through-hole connected copper mutual connection method, comprising the following steps of: forming a lower-layer copper metal layer and depositing one layer of medium film; carrying out photoetching to form a photoresist shielding part and a non-photoresist shielding part; etching a medium film of the non-photoresist shielding part; etching or corroding the lower-layer copper metal layer of an etched part of the medium film; depositing a metal interlayer film; carrying out photoetching to define a graph of an upper-layer copper metal layer with a groove; etching a medium layer of the groove in the graph of the upper-layer copper metal layer; and forming the upper-layer copper metal layer in the groove through a depositing and electroplating process. Photoetching and etching processes are finished on a plane and the communication of metal of upper and lower layers is realized by directly contacting two layers of copper, so that the negative influences on the processes by non-plane properties of an embedded structure are avoided and the controllability of the processes is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a copper interconnection method for non-through-hole connection in semiconductors. Background technique [0002] With the advancement of integrated circuit manufacturing technology, the interconnection part has more and more influence on the overall performance of the chip (including speed, area, power consumption, yield and reliability, etc.). An important progress in the development of interconnection technology is to replace aluminum with copper as the metal connection. On the one hand, it is determined by the material properties of copper, that is, the resistivity of copper is lower than that of aluminum, and the resistance to electromigration is also better. On the other hand, the damascene process (also known as "Damascus" process) used in copper interconnection can be better integrated with ultra-low-k value dielectrics to...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
Inventor 李铭
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT