MOS transistor effective channel length test structure and test method

Abstract

The invention relates to the field of semiconductor technology, and discloses a MOS transistor effective channel length test structure and test method, through the junction capacitance measurement of the PN junction first test unit and the MOS transistor second test unit with identical doping conditions, accurate The lateral diffusion length of doping in the active region of the MOS transistor is extracted, and then the effective channel length of the MOS transistor is accurately measured. In addition, in the test structure provided by the present invention, the active region of the MOS transistor is realized by the LDD process, and only the region below the contact hole in the active region is a heavily doped region, which reduces the influence of the heavily doped region on the measurement of the LDD lateral diffusion length. influence, making the measurement results more accurate. The testing structure and testing method provided by the invention have no specific dependence on the characteristic size of the MOS transistor, and can realize high-precision testing of the effective channel length of the small-sized MOS transistor.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to the effective channel length testing technology in MOS transistors. Background technique [0002] In MOS transistors, the channel length is an important basic parameter, which has an extremely important impact on the device performance of the MOS transistor and the design and manufacture of the entire integrated circuit. Therefore, the test and extraction of the effective channel length of the MOS transistor have always been Both are important topics in the field of MOS device research, especially as the size of semiconductor devices continues to shrink, the accurate measurement and extraction of effective channel lengths have more and more influence on MOS device and circuit performance evaluation, semiconductor device simulation modeling and design optimization. The importance of effective channel length testing is becoming more and more prominent. [0003] figure 1 It...

AI Technical Summary

Problems solved by technology

In this method, it is implicitly assumed that the inversion region capacitance C Gi and accumulation region capacitance C Ga are related to the gate voltage V gs irrelevant constant, and this assumption is only true for long-channel MOS transistors, for short-channel MOS devices, the accumulation region capacitance C Ga will increase with the gate-source voltage V gs changes, resulting in gate-channel capacitance C GC cannot be calculated accurately

Extract the effective channel length L by using the gate capacitance method eff The method has great limitations for small size devices

Images