Non-volatile semiconductor memory and manufacturing method thereof

Abstract

An enhanced non-volatile semiconductor memory has a source region and a drain region provided in a semiconductor substrate, an electric charge accumulating portion provided on a channel region between the source and drain regions and a control gate provided on said channel region and at least said source region is provided by introducing an impurity in self-alignment with a side wall provided on a side surface of said control gate, characterized in that an overlap of said drain region with said electric charge accumulating portion is set larger than an overlap of said source region with said electric charge accumulating portion, and an impurity dose quantity of said source region is larger than an impurity dose quantity of said drain region. The drain region may be formed by self alignment manner using a first side wall and the source region may be formed by self alignment manner using a second side wall formed on the first side wall.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates generally to an electrically erasable non-volatile semiconductor memory, and more particularly to a memory cell structure useful for a flash EEPROM of a NOR type etc., in which a writing operation is executed by injecting hot electrons. [0003] 2. Description of the Art [0004] A memory cell of an EEPROM (Electrically Erasable Programable Read Only Memory) normally involves the use of an FETMOS structure in which a floating gate and a control gate are stacked via an insulating film on a semiconductor substrate. [0005] Among a variety of EEPROMs, normally a hot electron injection is utilized in a NOR type flash memory cell. That is, in writing mode, the memory cell is set in on-state in which a large channel current flows. In this state, Hot electrons are thereby generated in a pinch-off region in the vicinity of a drain, and are injected into the floating gate. An erasing operation is car...

AI Technical Summary

Benefits of technology

The present invention provides a non-volatile semiconductor memory with a structure that can decrease the gate length while ensuring an effective channel length required. The memory cell includes a source region, a drain region, an electric charge accumulating portion, and a control gate. The overlap of the source region with the control gate is set to the minimum necessary to cause no offset, while the overlap of the drain region with the control gate is set larger than the source region. The method of manufacturing the non-volatile semiconductor memory includes steps of providing a control gate, providing a side wall insulating layer, providing a drain region, and providing a source region. The memory cell structure and the method of manufacturing provide a compact memory cell with a high programming efficiency.

Problems solved by technology

The progress of the technology of down scaling the semiconductor devices has been remarkable over the recent years, however, if making an attempt of attaining a high-integration EEPROM by use of the down scaling technology, there might arise a situation in which an effective channel length can not be ensured in the case of increasing the overlaps of the source and drain regions with the floating gate.

Furthermore, when trying to keeping the effective channel length Leff to some extent, a gate length L elongates corresponding to a proportion of the overlaps of the source and drain regions with the floating gate, and it is therefore difficult to reduce a size of the memory cell.

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