Test method for burr interference trigger chip latch-up effect

Abstract

The invention provides a test method for a burr interference trigger chip latch-up effect, and aims to test whether a chip has a trigger latch-up effect aiming at different high-frequency oscillation burr signals. During test, three parameters, namely a maximum peak voltage value, a maximum pulse width Twidth and the burr density of a burr pulse wave, are required to be selected as a test point; one test point executes one trigger latch-up effect test; different maximum peak voltage values, different maximum pulse widths Twidth and different burr densities are used as different test points; a plurality of test points are respectively used for executing the trigger latch-up effect test; and finally, three-dimensional burr trigger Latch-Up Test result distribution can be formed.

Description

technical field [0001] The invention relates to a test method for chip latch-up effect triggered by burr interference, in particular to a chip latch-up effect test suitable for high reliability requirements. Background technique [0002] At present, the basic method of testing the chip latch-up effect is clearly stipulated in the open international standard JEDEC IC Latch-Up Test JESD78B. [0003] Such as figure 1 As shown, there are three types of test trigger waveforms specified by JESD78B, which are intermittent positive current, negative current, and power supply overvoltage pulse waveforms. [0004] According to the standard IC Latch-Up Test JESD78B, the three kinds of trigger pulse waveforms have a pulse width of 10μs to 1s, the current trigger pulse amplitude is the normal working current plus 100mA or 1.5 times the normal working current, and the power supply overvoltage trigger pulse The magnitude is 1.5 times the normal operating supply voltage. [0005] In the ...

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Problems solved by technology

[0007] In this way, although some chips have passed the higher-level latch-up effect test according to the standard IC Latch-Up Test JESD78B, in actual use, they encounter interference sources such as lightning, relays, thyristors, motors, and high-frequency devices. The random high-frequency oscillating glitch waveform generated, but it is easy to trigger the latch-up effect

Obviously, the IC latch-up effect test specified in the standard IC Latch-Up Test JESD78B cannot meet the actual system application test requirements of the chip.

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