Transistor structure, shallow groove isolation structure and manufacturing method thereof
A technology of isolation structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of shrinking, unable to meet the design requirements of high-voltage components, etc.
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[0036] See Figure 1A to Figure 1J , which is a schematic diagram of the manufacturing method steps of the shallow trench isolation structure (Shallow Trench Isolation, referred to as STI) proposed by the present invention. First, as Figure 1A As shown, a silicon substrate 1 is provided, and a pad oxide layer 10 is formed on the surface of the silicon substrate 1 , and the silicon substrate 1 is divided into two regions, a high voltage device region 11 and a low voltage device region 12 .
[0037] Next, perform zero etch on the silicon substrate 1. The main purpose of the zero etch is to use a photomask photolithography etching process on the silicon substrate 1 to define alignment marks (alignment marks, Not shown in this figure), but in order to improve the known deficiencies, the present invention adds the pattern of the shallow trench isolation structure in the high-voltage element region 11 to the photomask pattern in the zero-layer etching, so that, Such as Figure 1B ...
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