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Transistor structure, shallow groove isolation structure and manufacturing method thereof

A technology of isolation structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of shrinking, unable to meet the design requirements of high-voltage components, etc.

Active Publication Date: 2013-03-06
UNITED MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, as the size of components in low-voltage logic circuits shrinks with technological progress, the width and depth of shallow trench isolation structures are also miniaturized. When the size of the shallow trench isolation structure in the logic circuit is the same, it may not be able to meet the design requirements of high-voltage components, and how to improve the deficiency of this known method is the main purpose of the development of the present invention

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  • Transistor structure, shallow groove isolation structure and manufacturing method thereof
  • Transistor structure, shallow groove isolation structure and manufacturing method thereof
  • Transistor structure, shallow groove isolation structure and manufacturing method thereof

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Embodiment Construction

[0036] See Figure 1A to Figure 1J , which is a schematic diagram of the manufacturing method steps of the shallow trench isolation structure (Shallow Trench Isolation, referred to as STI) proposed by the present invention. First, as Figure 1A As shown, a silicon substrate 1 is provided, and a pad oxide layer 10 is formed on the surface of the silicon substrate 1 , and the silicon substrate 1 is divided into two regions, a high voltage device region 11 and a low voltage device region 12 .

[0037] Next, perform zero etch on the silicon substrate 1. The main purpose of the zero etch is to use a photomask photolithography etching process on the silicon substrate 1 to define alignment marks (alignment marks, Not shown in this figure), but in order to improve the known deficiencies, the present invention adds the pattern of the shallow trench isolation structure in the high-voltage element region 11 to the photomask pattern in the zero-layer etching, so that, Such as Figure 1B ...

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Abstract

The invention discloses a transistor structure, a shallow groove isolation structure and a manufacturing method thereof. The manufacturing method comprises the following steps of: providing a baseplate, wherein a high voltage element region is defined on the baseplate; utilizing a first etching process to manufacture a pretreating shallow groove in the high voltage element region; utilizing a second etching process to sequentially etch the pretreating shallow groove in the high voltage element region into a first shallow groove; and filling a dielectric material in the first shallow groove to form a first shallow groove isolation structure.

Description

technical field [0001] The invention relates to a transistor structure, a shallow trench isolation structure and a manufacturing method thereof, in particular to a shallow trench isolation structure and a manufacturing method thereof applied in semiconductor technology. Background technique [0002] Completing the design of low-voltage logic circuits and high-voltage components on the same integrated circuit chip is the mainstream of today's integrated circuit production. Regardless of low-voltage logic circuits or high-voltage components, isolation components must be fabricated to electrically isolate components. Shallow Trench Isolation (STI) is currently the most commonly used isolation element, and the shallow trench isolation structure in low-voltage logic circuits and high-voltage elements is usually completed in the same process. [0003] However, as the size of components in low-voltage logic circuits shrinks with technological progress, the width and depth of shall...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L21/762H01L29/78H01L29/06
CPCH01L29/0653H01L29/7816H01L29/7833
Inventor 黄良安黄钰钧林进福林郁乔林裕杰刘信良郑钧鸿杨渊丞许尧凯
Owner UNITED MICROELECTRONICS CORP