Method for parametrically generating multi-strength driving unit

Abstract

The invention provides a method for parametrically generating a multi-strength driving unit. The method comprises the following steps of: a) preparing a territory of a unit-strength driving unit, wherein active regions on the two sides of the unit-strength driving unit are configured to be capable of being directly connected; b) receiving the input parameter of the quantity of the unit-strength driving units in the designated multi-strength driving unit; and c) sequentially connecting the unit-strength driving units in the quantity designated by the input parameter to form the territory of the multi-strength driving unit. Since a high-driving-capacity unit is realized through parametrically programmable units, the territory of the unit can be generated by setting a series of input parameters. Moreover, since the active regions in the generated territory are directly connected, compact layout design is obtained.

Description

technical field [0001] The present invention relates to the field of integrated circuit design, in particular to a method for parametrically generating multiple-intensity drive units. Background technique [0002] In the semi-customized ASIC (Application Specific Integrated Circuit) design, the standard cell library provides the designer with a link between the actual chip and the designed circuit implementation. For digital circuit design, especially for large-scale digital circuit design in the nanotechnology stage, the standard cell library has become a necessary condition for the design. Every stage after synthesis is inseparable from the support of the standard cell library. Refer to figure 1 . [0003] In the current SoC (System on Chip) design, the scale of the circuit is very large, and the output of one unit is often connected to many units, resulting in a large fan-out of the unit, which requires the unit to have a strong driving capability. At the same time, the...

AI Technical Summary

Problems solved by technology

Although this method can realize the multi-drive capability of the unit, due to the constraints of the design rules, there must be sufficient spacing between the units connected in parallel, which will undoubtedly cause a waste of chip area.

Also, it is a lot of work to make lookup tables that contain delay information for cells implemented in this way

This will delay the release of the cell library, which in turn will affect the time to market of the product

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