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Excessive Loop Delay Compensation for Continuous-Time Sigma‑Delta Modulators

A loop delay and circuit technology, applied in the field of sigma-delta modulators, can solve problems such as excessive delay and instability

Active Publication Date: 2017-06-06
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This arrangement has some disadvantages; namely, parasitic poles and / or unaccounted for excessive delays (which may exist due to parasitic poles or paths) can lead to unstable behavior

Method used

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  • Excessive Loop Delay Compensation for Continuous-Time Sigma‑Delta Modulators
  • Excessive Loop Delay Compensation for Continuous-Time Sigma‑Delta Modulators
  • Excessive Loop Delay Compensation for Continuous-Time Sigma‑Delta Modulators

Examples

Experimental program
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Embodiment Construction

[0025] Reference is now made to the drawings in which, for the sake of clarity, described elements are not necessarily shown to scale, and in which the same or similar elements are designated by the same reference numerals throughout the several views.

[0026] To understand some of the problems associated with the SDM 100, a performance analysis can be performed. Since SDM 100 is a continuous time SDM, there are inherent difficulties in analyzing its performance because sampling is performed within the feedback loop of SDM 100 . Therefore, you can use figure 2 The discrete-time SDM equivalent model is shown, and further for the purpose of simplifying the analysis, the comparator 106 may be a 1-bit comparator. In this model, H(s) represents the filter corresponding to the integrator (ie, integrator pipeline 114), and H(s) d (s) represents the filter corresponding to the DAC (ie, 110-1). In addition, since there are delays within the loop, blocks ELD and ID are also include...

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Abstract

Provide a method and corresponding equipment. In operation, an integrator is used to integrate an analog signal to produce an integrated analog signal. The integrated analog signal is compared with a reference voltage using a plurality of comparators in synchronization with the first clock signal and the second clock signal to generate a comparator output signal. Subsequently, a feedback current is generated from the comparator output signal in synchronization with the second clock signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched synchronized with the first clock signal to produce a latched output signal. This latched output signal is converted into a feedback analog signal, and the difference between the analog signal and the feedback analog signal is determined.

Description

technical field [0001] The present invention relates generally to sigma-delta modulators (SDMs) and, more particularly, to excessive loop delays (ELDs) of SDMs. Background technique [0002] Turning to Figure 1, a conventional SDM 100 can be seen. This SDM 100 generally includes an integrator pipeline 114 (which generally includes stages 112 - 1 through 112 -N coupled in series with each other), a comparator 106 , and a latch 108 . Each of stages 112-1 through 112-N generally includes adders 102-1 through 102-N (which are typically one node of a single-ended SDM and a pair of nodes of a differential SDM), an integrator 104-1 to 104-N, and digital-to-analog converters (DACs) 110-1 to 110-N. In operation, the integrator pipeline 114 (which facilitates forming the Nth order SDM) generally integrates the analog signal IN so that the comparator 106 can compare the integrated analog signal IN to one or more reference voltages. Typically, the comparator 106 includes several latc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M3/00H03M1/06
CPCH03M3/37H03M3/424H03M3/454
Inventor 文卡特什·斯里尼瓦桑帕特里克·萨塔尔扎德维多利亚·王 林凯特凯巴赫尔·哈龙马尔科·科西
Owner TEXAS INSTR INC