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A method and device for realizing optimal master clock algorithm

A technology of optimal master clock and implementation method, applied in time division multiplexing system, digital transmission system, data exchange network, etc., can solve the problems of poor clock recovery performance, heavy load, network turbulence, etc.

Active Publication Date: 2017-07-21
ZTE CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the standard BMC algorithm, the active GM clock will carry loads as much as possible (as long as these loads can directly or indirectly see the active GM), and this makes the standby GM unable to function, and can only fail when the active GM It will assume the role of its GM, which leads to excessive load around the active GM, too many hops, and poor performance of clock recovery; moreover, when the network performs active-standby GM switchover, all loads need to be Switching caused large-scale turbulence in the network and introduced time jitter

Method used

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  • A method and device for realizing optimal master clock algorithm
  • A method and device for realizing optimal master clock algorithm
  • A method and device for realizing optimal master clock algorithm

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Embodiment Construction

[0042] This embodiment provides a method for implementing the best master clock (BMC) algorithm, specifically including the following main contents:

[0043] 1. The multi-GM algorithm control parameter multi-GM model is introduced: the user can switch between the standard algorithm and the extended algorithm by configuring this parameter.

[0044] 2. Introduced the local clock class (clockclass) limit parameter class-limit: Whether to switch to the clock class value of the standard GM mode, this value is configured by the user.

[0045]In practical applications, there may be such requirements: when multiple GM clocks in the network have high performance, so that the deviation between each GM can be ignored, it is hoped that multiple GMs can survive and jointly maintain the network and share the load; but when the network After the clock quality of the GMs in the network drops to a certain level, there may be large deviations among the GMs. At this time, it is hoped that the ne...

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Abstract

The invention discloses a method and a device for realizing a best master clock algorithm. The method comprises the following steps of: firstly comparing whether clock ids (identifications) of an external clock and a local clock are the same when comparing clock data sets; if clock ids are different, then comparing the clock performances of the external clock and the local clock; if the clock performances of the external clock and the local clock are consistent, determining whether to enter a multiple GM (grand master clock) mode; and if determining to enter the multiple GM mode, comparing hop counts of two clock data sets. When the hop counts are unequal, the data set with less hop count is better than the data set with larger hop count, and when the hop counts are equal, a better data set is determined by comparing clock ids or random selection. By utilizing the method and the device, survival of a plurality of GM clocks with the same clock performance in a domain is realized, and load can be reasonably distributed according to a shortest hop count manner.

Description

technical field [0001] The invention relates to the technical field of clock synchronization communication networks, in particular to a method and device for realizing an optimal master clock algorithm. Background technique [0002] With 3G (The 3 rd Generation, the third generation of mobile communication technology) the rapid development of the network, the PTP time synchronization protocol has been paid more and more attention and widely used in the communication network. Domestic and foreign operators continue to use the Precision Time Synchronization Protocol (Precision Time Protocol, PTP for short) for time synchronization, and gradually replace the method of using GPS (Global Positioning System, Global Positioning System) for time synchronization. [0003] In the IEEE 1588V2 protocol, under the multicast networking, the network topology is controlled through the BMC algorithm (Best MasterClock Algorithm, best master clock algorithm). The standard BMC algorithm come...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06H04L12/24
CPCH04J3/0641H04J3/0667
Inventor 赵洪广夏靓
Owner ZTE CORP
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