A fast loading method for satellite navigation receiver fpga

Abstract

The invention relates to a satellite navigation receiver FPGA (Field Programmable Gate Array) rapid loading method. According to the method, a multifutional buffer serial port of a DSP (Digital Signal Processor) chip is adopted as a special clock data line special for an FPGA during loading by virtue of a special use metod; the DXm of the multifunctional buffer serial port is used as a data line to be connected with an FPGA loading data input end DATA0; the CLKXm of the multifunctional buffer serial port is used as a clock line to be connected with an FPGA loading data input end DCLK; and the GPIO (General Purpose Input / Output) pin of the DSP is used as a loading functional line to be connected with three special deployment pins of the FPGA. According to the method, the DSP chip, a FLASH chip, an RS232 level conversion chip, resisters R1, R2 and R3, and the FPGA are firstly connected, then FPGA loading is performed, and remote upgrading is performed on a FLASH program according to needs; and the method has the advantages of short loading time, easiness for external program upgrading, large storage capacity, rapid loading speed, less possibility of electromagnetic interference and strong universality.

Description

technical field [0001] The invention belongs to the technical field of positioning, navigation and control, and in particular relates to a fast loading method for a satellite navigation receiver FPGA. Background technique [0002] The FPGA chip in the satellite navigation receiver is used as the core device to realize important functions such as capturing and tracking satellite signals. Every time the receiver is powered on, the FPGA chip needs to be loaded with programs, and the loading time has a great impact on the startup time of the receiver. The invention mainly solves the problem that the loading time of the FPGA program of the satellite navigation receiver is too long. The FPGA program loading in the satellite navigation receiver usually adopts the serial passive loading mode or the active loading mode using a dedicated loading chip. The serial passive loading mode uses the general IO pins of the DSP chip as the dedicated loading clock data lines for the FPGA, and t...

AI Technical Summary

Problems solved by technology

The serial passive loading mode uses the general IO pins of the DSP chip as the dedicated loading clock data lines for the FPGA, and the FPGA program is stored in the external FLASH. This method is limited by the access speed of the general IO pins. It takes 6 hours to load a 2M byte program. seconds, slower

Using a dedicated loading chip to actively load, the speed is faster, and it takes 0.9 seconds to load a 2M byte program, but this method requires a dedicated loading chip to program the FPGA program using the JTAG interface of the FPGA chip. After the satellite navigation receiver is assembled, the FPGA is led out There are difficulties in connecting the JTAG port of the chip to the external connector, and the JTAG port leading out is susceptible to external electromagnetic interference, which affects the normal operation of the receiver

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