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Priority adjustable multiple-channel direct memory access (DMA) controller

A DMA controller and channel control technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problem of limited number of DMA channels and achieve the effect of enhancing versatility

Inactive Publication Date: 2013-04-24
BEIJING INST OF STRUCTURE & ENVIRONMENT ENG +3
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] As a mechanism for fast data transmission, DMA solves the data transmission between peripherals and memory well, but the number of DMA channels in the main control device of the microprocessor (microprocessor unit, MPU) is often very limited
For high-speed multi-channel data acquisition systems, it is difficult to allocate a DMA channel for each data channel to store data

Method used

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  • Priority adjustable multiple-channel direct memory access (DMA) controller
  • Priority adjustable multiple-channel direct memory access (DMA) controller
  • Priority adjustable multiple-channel direct memory access (DMA) controller

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Embodiment Construction

[0027] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

[0028] A block diagram of the system composition of a priority-adjustable multi-channel DMA controller provided by the present invention is as follows: figure 1 shown. The MPU can complete the dynamic configuration of the adjustable multi-channel DMA controller through the instruction setting and the register group addressed uniformly with the memory.

[0029] Such as figure 1 Shown:

[0030] The register file 1 includes eight register groups: that is, the first channel register group 101, the second channel register group 102, the third channel register group 103, the fourth channel register group 104, the fifth channel register group 105, and the sixth channel register group Group 106 , seventh channel register group 107 , eighth channel register group 108 .

[0031] Data input channel 2 includes eight data channels: first data input cha...

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Abstract

The invention belongs to a direct memory access (DMA) controller, and particularly discloses a priority adjustable multiple-channel DMA controller which comprises a data buffering storage and control module, a group of control registers and a multiplexing module, wherein the number of data input channels of the data buffering storage and control module and the group of the control registers are identical, the multiplexing module is used for communication of the data buffering storage and control module and used for transmitting signals and data, of the data buffering storage and control module, after being multiplexed to a DMA engine. Data transmitting task is achieved by the DMA engine according to working modes configured by the data inputting channels and a preset priority. Sharing one DMA data channel by a plurality of data inputting channels can be achieved through the DMA controller.

Description

technical field [0001] The invention belongs to a DMA controller, in particular to a multi-channel DMA controller with adjustable priority. Background technique [0002] In a data processing system and an SoC chip with a microprocessor (microprocessor unit, MPU) as the main control device, data transmission usually adopts three methods. 1) Polling mode: The MPU periodically detects the status of the slave device, and takes out data from the source device at an appropriate time and writes it into the destination device. When using this method, it will take a lot of processor time, and the data transmission speed is limited by the execution time of MPU instructions. 2) Interrupt mode: When the slave device needs to transmit data, it sends an interrupt request to the MPU, and the MPU executes the data transmission task after responding. When using this method, the MPU does not have to actively query the status of the slave device, which saves part of the processor time, but t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/30
Inventor 房远勇吕俊宋慧于宏伟袁怡诤叶重林丁竹生
Owner BEIJING INST OF STRUCTURE & ENVIRONMENT ENG