Manufacturing method for rewiring quad flat no-lead (QFN) packaging component

Abstract

The invention discloses a manufacturing method for a rewiring quad flat no-lead (QFN) packaging component. A chip carrier and lead feet of the manufactured rewiring QFN packaging component are formed by using of an etching method in the process of packaging technology. Insulating filling materials are arranged between the chip carrier and the lead feet, and in grooves between the lead feet by using an injection molding method or a silk-screen printing method. Rewiring layers are manufactured by using of electroplating and chemical plating methods and are packaged by using of plastic package materials. After the process of plastic package, an independent chip carrier and independent lead feet are formed by using of the etching method or a mechanical grinding method. The manufactured rewiring QFN packaging component is high in input / output (I / O) density, low in manufacturing cost and good in reliability.

Description

technical field [0001] The invention relates to the technical field of manufacturing QFN components, in particular to a quadrilateral flat no-lead package with high I / O density and a manufacturing method thereof. Background technique [0002] With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portability, ultra-thinness, multimedia and low-cost requirements for popularization, high-density, high-performance, high-reliability and low-cost packaging forms and Its assembly technology has been developed rapidly. Compared with expensive BGA and other packaging forms, the new packaging technology developed rapidly in recent years, that is, Quad Flat Non-lead Package (QFN) package, has good thermal and electrical properties, small size, Many advantages such as low cost and high productivity have triggered a new revolution in the field of microelectronic packaging technology. [0003] Due to the improvement of IC integ...

AI Technical Summary

Problems solved by technology

However, in order to increase the number of I / Os of QFN packaged devices, more areas are needed to place multiple pins, so the size of QFN packaged devices needs to be increased, which is contrary to the requirements of miniaturization of packaged devices, and with the package As the size increases, the distance between the chip and the pins will increase, resulting in an increase in the use of metal wires, such as gold (Au) wires, which increases manufacturing costs. Too long metal wires can easily cause metal wires during the injection molding process. Problems such as collapse, line punching, and crossing lines affect the improvement of the yield and reliability of packaged devices

Therefore, in order to break through the oversized bottleneck of the existing multi-turn pin arrangement QFN package device, solve the above-mentioned yield and reliability problems and reduce manufacturing costs, it is urgent to develop a small size, high reliability, low cost, high QFN package device with I / O density and manufacturing method thereof

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