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Loading treatment circuit, method and system

A processing circuit, low-level technology, applied in the direction of program loading/starting, program control devices, etc., can solve the problems of reducing loading efficiency and long loading time, and achieve the effect of improving efficiency and solving long loading time

Active Publication Date: 2013-05-01
南通三聚知识产权服务有限公司
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Problems solved by technology

[0003] In the process of realizing the embodiment of the present invention, the inventor found that in the prior art, when loading the storage device by scanning the controller in the JTAG device, it is necessary to scan each pin of the JTAG device, and control each pin The 0, 1 sequence of the pin completes the program loading process of the SPI FLASH storage device, which causes the problem of long loading time and reduces the loading efficiency

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  • Loading treatment circuit, method and system
  • Loading treatment circuit, method and system
  • Loading treatment circuit, method and system

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Embodiment Construction

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0045] figure 1 A schematic diagram of the architecture of the JTAG system based on the loading processing circuit of the present invention, such as figure 1 As shown, the JTAG system includes: a processor 111 and a JTAG master node 112 on the system main control board 11 , and a JTAG slave node 121 and a JTAG device 122 on the device service boa...

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Abstract

The embodiment of the invention provides a loading treatment circuit, a method and a system. The loading treatment circuit comprises a channel selection module and a time-sequence conversion module, wherein the channel selection module is respectively connected with a controller, a joint test action group (JTAG) slave node and storage equipment and is used for respectively connecting the controller or the JTAG slave node with the storage equipment when a reset signal in the JTAG slave node is at low level or is at high level; the time-sequence conversion module is respectively connected with the JTAG slave node and the channel selection module and is used for carrying out time-sequence conversion treatment on a transportation management system (TMS) signal output by a TMS interface in the JTAG slave node; and when the reset signal in the JTAG slave node is at the high level, the TMS signal after the time-sequence conversion treatment is output to a low-level effective control system (CS) interface of the storage equipment. According to the embodiment of the invention, the operation of loading treatment can be carried out on the storage equipment according to a transport driver interface (TDI) signal and a technology compatibility kit (TCK) signal of the JTAG slave node and the TMS signal after the time-sequence conversion treatment.

Description

technical field [0001] Embodiments of the present invention relate to semiconductor technology, and in particular to a loading processing circuit, method and system. Background technique [0002] The Joint Test Action Group (JTAG) is mainly used in boundary scan testing of circuits and in-system programming of programmable chips. When the JTAG device has an external storage device, such as a serial peripheral interface (Serial Peripheral Interface, hereinafter abbreviated as SPI) flash (FLASH) storage device and other devices, the storage device can be loaded by scanning the controller in the JTAG device. [0003] In the process of realizing the embodiment of the present invention, the inventor found that in the prior art, when loading the storage device by scanning the controller in the JTAG device, it is necessary to scan each pin of the JTAG device, and control each pin The 0, 1 sequence of the pin completes the program loading process of the SPI FLASH storage device, wh...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/445
Inventor 梅优良
Owner 南通三聚知识产权服务有限公司