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Information processing method and device

An information processing method and technology for an information processing device, which are applied in the fields of electrical digital data processing, memory address/allocation/relocation, instruments, etc., can solve problems such as bottlenecks restricting processing speed, limited overall performance of system chips, and memory access speed, etc. Achieve the effect of improving the overall processing speed, saving chip area and chip power consumption, and improving the reading speed

Active Publication Date: 2016-07-13
GALAXYCORE SHANGHAI
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Problems solved by technology

[0005] The inventors found that: in the existing System-on-a-chip (SoC), especially in the system chips that occupy a large memory bandwidth, the blocking of the cache memory has become a bottleneck restricting the processing speed, which makes The overall performance of the SoC is limited by the access speed of the memory

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Embodiment Construction

[0063] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

[0064] Secondly, the present invention is described in detail by means of schematic diagrams. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams are only examples, which should not limit the protection scope of the present invention.

[0065] In order to solve the technical problems in the background art, the present invention provides an information processing method, which is suitable for a prefetchable cache. figure 1 It is a schematic flowchart of t...

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Abstract

The invention discloses an information processing method and device, which are suitable for pre-fetching caching. The information processing method comprises the following steps of: acquiring the information of data to be read according to an external reading command, and determining missing data in a cache memory according to the information of the data to be read and mark information of the cache memory; sequencing the missing data to form a reading command queue and a corresponding filling command queue; reading the missing data from an off-chip memory in sequence according to the reading command queue; and filling the missing data into the cache memory according to the filling command queue. The information processing device comprises the cache memory, a microprocessor, a first transient memory for storing the reading command queue, and a second transient memory for storing the filling command queue. According to the invention, the congestion phenomenon of the cache memory can be avoided or reduced, so that the processing speed of a chip can be improved.

Description

technical field [0001] The invention relates to the field of digital information processing, in particular to a prefetchable information processing method and device. Background technique [0002] During the development of computer technology, the access speed of memory has always been much slower than the processing speed of CPU, so that the high-speed processing capability of CPU cannot be fully utilized, affecting the work efficiency of the entire computer system. Cache memory is used to alleviate the speed mismatch between CPU and memory. The use of high-speed cache memory technology has been quite common. The high-speed cache memory is a first-level memory that exists between the memory and the CPU. It is composed of a static memory chip (SRAM) and has a relatively small capacity, but its access speed can match the CPU. According to the principle of program locality, there is a high probability that those units adjacent to a unit of memory being used will be used. Th...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08G06F12/0862
Inventor 兰军强朱磊沙力李济川
Owner GALAXYCORE SHANGHAI
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