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Online upgrading structure and method for FPGA chip based on data frame asynchronous transmission protocol

An asynchronous transmission and data frame technology, applied in the direction of electrical digital data processing, instruments, program control devices, etc., can solve the problems that software and hardware cannot be upgraded, and the program of updating chips is complicated and difficult to implement, so as to achieve stable and reliable working performance and wide application range Wide, fast-running effects

Active Publication Date: 2013-05-15
SHANGHAI WEIHONG ELECTRONICS TECH
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The existing online update mainly exists in the local area network, and generally can only update the application software on the PC, and cannot upgrade the software and hardware of the deeper layer (chip level); while the program for updating the chip through the traditional download interface is more complicated Difficult to implement in various fields
This will bring all kinds of inconvenience to people's work.

Method used

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  • Online upgrading structure and method for FPGA chip based on data frame asynchronous transmission protocol
  • Online upgrading structure and method for FPGA chip based on data frame asynchronous transmission protocol
  • Online upgrading structure and method for FPGA chip based on data frame asynchronous transmission protocol

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Embodiment Construction

[0081] In order to understand the technical content of the present invention more clearly, the following examples are given in detail.

[0082] see Figure 1 to Figure 7 As shown, the circuit structure based on the data frame asynchronous transmission protocol to realize the online upgrade of the FPGA chip includes a control card, a main terminal board and several slave terminal boards, and the control card, the main terminal board and each slave terminal board all carry FPGA chip and corresponding Flash memory are arranged, and described control card is connected with external computer, and described control card, master terminal board and several slave terminal boards are serially connected successively, wherein, described control card carries The host interface and the slave interface, the main terminal board carries the main terminal board host interface and the main terminal board slave interface, and each of the slave terminal boards carries its own slave terminal board ...

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Abstract

The invention relates to an online upgrading structure for an FPGA (Field Programmable Gate Array) chip based on a data frame asynchronous transmission protocol. The host interface of a control card is connected with an external computer; the slave interface of the control card is connected with the host interface of a main terminal board; the slave interface of the main terminal board is connected with the host interface of a slave terminal board; and the slave interface of the slave terminal board is connected in series with the rest of slave terminal boards in sequence. The invention further relates to an online upgrading method for the FPGA chip based on the data frame asynchronous transmission protocol. The online upgrading structure and method adopting the structure can be used for dealing with errors occurring in the updating process and guaranteeing the updating process to be smoothly and reliably performed so as to successfully solve the problem that the conventional bottom layer cannot be updated or the updating process is complex and difficult to implement, and are simple, reliable, convenient, easy, higher in running speed, better in extendability, stable and reliable in working performance and wider in application range.

Description

technical field [0001] The invention relates to the field of FPGA chips of programmable logic devices, in particular to the field of FPGA chip online update and upgrade control technology, and specifically refers to a circuit structure and a control method for realizing online upgrade of FPGA chips based on a data frame asynchronous transmission protocol. Background technique [0002] Now most FPGA chips are based on RAM, and their programs are stored in the external FLASH memory. Users generally download and debug the programs through the JTAG download interface. [0003] The existing online update mainly exists in the local area network, and generally can only update the application software on the PC, and cannot upgrade the software and hardware of the deeper layer (chip level); while the program for updating the chip through the traditional download interface is more complicated It is difficult to realize in various fields. This has brought various inconveniences to peo...

Claims

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Application Information

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IPC IPC(8): G06F13/20G06F9/445
Inventor 王少阳邓美龙汪定军郑之开汤同奎
Owner SHANGHAI WEIHONG ELECTRONICS TECH
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