Bypass structure of static random access memory (SRAM)

Abstract

The invention discloses a bypass structure of a static random access memory (SRAM). The bypass structure of the SRAM comprises two negation gates and two three-port alternative denial gates, wherein input ends of the two negation gates are respectively connected with a written-in data signal pair, one input ends of two three-input alternative denial gates are respectively connected with output ends of the two negation gates, and another input ends of two three-input alternative denial gates are respectively connected with a read data signal pair, and another input ends of two three-input alternative denial gates are respectively connected with an output end of another three-input alternative denial gate. The bypass structure of the SRAM is provided with a simple circuit structure, a few of metal oxide semiconductor transistors are needed when the bypass structure of the SRAM is used in a semiconductor integrated circuit, the area of an SRAM element is saved, and therefore energy consumption of the SRAM element is lowered.

Description

Technical field [0001] The present invention relates to an SRAM (static random access memory), in particular to a bypass structure of SRAM. Background technique [0002] Operations on SRAM include writing data and reading data. When writing data to the SRAM, if the data at its input end is reflected to its output end as it is, this function is called a bypass function, and the structure that realizes this function is called a bypass structure. [0003] See figure 1 , This is the signal diagram of SRAM. Wherein DIN represents the input signal of the data. DOUT represents the output signal of data. CLK represents a clock signal, and its rising edge is valid. WEN represents the write enable signal. When it is low level (0), it means data is written into SRAM. At this time, the output signal DOUT needs to copy the input signal DIN; when it is high level (1), it means reading data from SRAM. [0004] figure 1 When the write enable signal WEN is low level, the input data DIN is DATA1,...

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Problems solved by technology

However, due to the read operation while writing, the power consumption is relatively large, which is different from the figure 2 The implementation circuit with multiple MOS transistors shown consumes about the same

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