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Power saving method of dynamic memory under read operation and column selection signal driving circuit of dynamic memory

A technology of dynamic memory and column selection signal, applied in static memory, digital memory information, information storage and other directions, can solve problems such as power waste, and achieve the effect of solving power waste and reducing power consumption

Active Publication Date: 2013-06-26
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The invention provides a power saving method and a column selection signal driving circuit of a dynamic memory read operation, which solves the problem of waste of electric energy during the read operation of the dynamic memory, so as to effectively reduce the power consumption of the dynamic memory

Method used

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  • Power saving method of dynamic memory under read operation and column selection signal driving circuit of dynamic memory
  • Power saving method of dynamic memory under read operation and column selection signal driving circuit of dynamic memory
  • Power saving method of dynamic memory under read operation and column selection signal driving circuit of dynamic memory

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Embodiment Construction

[0017] Embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0018] see Figure 5 and Figure 6 As shown, a column selection signal driving circuit of a dynamic memory in the present invention includes PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, NMOS transistor M4, NMOS transistor M5, NMOS transistor M6 first inverter inv1 and second inverter Phaser inv2.

[0019] The input terminal of the second inverter inv2 is connected to the amplification enabling signal line CMA of the second-stage sense amplifier SSA, and the output terminal of the second inverter inv2 is connected to the gate of the PMOS transistor M3 through the reverse amplification enabling signal line CMA_N and the gate of the NMOS transistor M6. The gate of the PMOS transistor M1 and the gate of the NMOS transistor M4 are connected to the CSL decoding circuit enable signal input line csle; the gate of the PMOS transistor M2 and the ...

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Abstract

The invention provides a power saving method of a dynamic memory under read operation and a column selection signal driving circuit of the dynamic memory. The power saving method comprises the following steps of: an amplification enabling signal of a second-stage sensitive amplifier or an equalizing signal of the second-stage sensitive amplifier is high, and the second-stage sensitive amplifier in the dynamic memory works, a switch between a low closing bit line and partial data lines is turned off according to a column selection signal. By the power saving method, the problem of waste of electric energy during read operation of the conventional dynamic memory is solved, and the power consumption of the dynamic memory can be effectively reduced.

Description

【Technical field】 [0001] The invention relates to the technical field of dynamic memory, in particular to a method for saving power under read operation of the dynamic memory and a column selection signal driving circuit thereof. 【Background technique】 [0002] Such as figure 1 As shown, when the dynamic memory is in the read operation, the column selection signal of the column selection signal line CSL opens the switch between the bit line (BL / BL_N) and the local data line (LDQ / LDQ_N), because the local data line (LDQ / LDQ_N ) and the total data line (MDQ / MDQ_N) The total data switch MDQS between the ACTIVE operation has already been opened, so one of the signal of the positive signal line MDQ of the data bus and the signal of the negative signal line MDQ_N of the data bus will be positive The bit line BL or the negative bit line BL_N is pulled low, so that there is a voltage difference between the positive signal line MDQ of the data bus and the negative signal line MDQ_N ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/407
Inventor 段会福俞冰付妮
Owner XI AN UNIIC SEMICON CO LTD
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