ddr2 read and write operation digital delay chain process-temperature-voltage controller circuit

Abstract

The invention discloses a DDR2 read-write operation digital delay chain technology-temperature-voltage controller circuit. Commands transmitted between a DDR2 controller and a DDR 2 memory are detected; a synchronous digital delay chain enable signal is output to a DDR2 read-write operation digital delay chain controller; and when a DDR2 controller command detector detects a refresh command, a technology-temperature-voltage controller circuit outputs a refreshed DDR2 read-write operation digital delay chain enable signal to the DDR2 read-write operation digital delay chain controller in the premise of locking of a DDR2 read-write operation digital delay chain. In DDR2 controller command refreshment, DQS and DQ signals are in an ineffective state and safe, reliable and high-precision DDR2 read-write operation digital delay chain dynamic refreshment is realized.

Description

technical field [0001] The present invention relates to the application of DDR2 (Double Data Rate, double rate synchronous dynamic random access memory) digital delay chain controller circuit for read and write operations, such as DDR, DDR2, DDR3, etc., which belong to the high-speed DDR2 read and write operation digital delay chain controller circuit technology field. Background technique [0002] With the continuous improvement of the performance of the system-on-chip SOC chip, the data throughput is also increasing, making the DDR2 (Double Data Rate, double-rate synchronous dynamic random access memory) controller more and more widely used. [0003] When the chip changes in process, temperature and voltage, the existing DDR2 read and write operation digital delay chain controller technology uses a dynamic update of the read and write operation digital delay chain, and does not take into account the DQ and DQS between the DDR2 controller and the DDR2 memory. state. The d...

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Problems solved by technology

[0004] 1. During the write operation of the DDR2 controller, the data DQ signal is completed in the write operation clock domain. This clock is the clock obtained by delaying the system DDR2 clock by 3 / 4 through the write operation clock digital delay chain. If the existing DDR2 The write operation clock digital delay chain controller dynamically adjusts the write operation clock, especially when adjusting the write operation digital delay chain near the positive and negative edges of the write operation clock, the write operation clock may have glitches, the period may decrease, and the data DQ signal is valid The time is reduced, and in severe cases, the data DQ may not meet the time window required by the DDR2 specification;

[0005] 2. During the write operation of the DDR2 controller, the DDR2 memory receives DQ data in the DQS clock domain of the write operation. This clock has the same phase as the DDR2 system clock ddr2_clk. If the DDR2 write operation is controlled according to the existing DQS digital delay chain The device dynamically adjusts the write operation DQS signal, especially when the write operation DQS is near the positive and negative edges, the write operation DQS may have glitches, the cycle may be reduced, and the effective time of the DQS signal is reduced. In severe cases, DQS may not meet the requirements of the DDR2 specification time window;

[0006] 3. During the read operation of the DDR2 controller, the DDR2 controller receives data in the DQS clock domain of the read operation. This clock is the clock obtained by delaying the DQS signal sent by the DDR2 memory by 1 / 4 of the phase of the DQS digital delay chain of the read operation. If According to the existing DDR2 read operation DQS digital delay chain controller dynamically adjusts the read operation DQS signal, especially when the read operation DQS is near the positive and negative edges, the read operation DQS may have glitches, the cycle may be reduced, and the effective time of the DQS signal is reduced. Small, resulting in a problem with the sampling DQ of the read operation DQS after the delay. In severe cases, the DQS of the read operation may not meet the time window required by the DDR2 specification

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