A method and device for protecting internal configuration memory of fpga chip

Abstract

The invention discloses a method, a chip and a device for protecting data of an FPGA (field programmable gate array) internal configuration memory. The method includes deciphering externally inputted enciphered data used for configuring the chip by deciphering codes; receiving an externally inputted user code; enciphering an access code by the deciphering code and taking a enciphered result as an access permission code when the access code is needed to be enciphered according to instructions of forced ciphering control bits, or , taking the access code directly as the access permission code; and comparing the inputted user code with the access permission code, and giving access permission of the configuration memory to a user when comparison results are consistent.

Description

technical field [0001] The invention relates to the field of memory, in particular to a method and device for protecting the internal memory of a programmable chip. Background technique [0002] Programmable chips have great flexibility. With the development of technology, its confidentiality performance is also becoming more and more important, especially FPGA (Field Programmable Gate Array, Field Programmable Gate Array) chips have higher and higher requirements for confidentiality. FPGA generally adopts SRAM (Static RAM, Static Random Access Memory) technology. The internal configuration registers and memory are not non-volatile, and a non-volatile memory needs to be connected externally. When the chip is powered on, it is read from the above-mentioned non-volatile memory. Configure the data to make the chip work. [0003] The above-mentioned non-volatile memory is relatively easy to be copied illegally because it is outside the chip. For this, the FPGA chip generally u...

AI Technical Summary

Problems solved by technology

[0008] It can be seen that at the beginning of FPGA power-on, the permission of JTAG interface to access the internal registers / memory of the chip is enabled by default, which is not conducive to the protection of internal registers / memory from the beginning; It is not easy for legitimate users to access the chip through the JTAG interface; because the data in the external non-volatile memory that controls access rights is easily deleted or tampered with, it is not enough to prevent the JTAG interface from illegally accessing the internal registers / memory of the FPGA chip

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