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Programmable Controllers

A programming controller and memory technology, which is applied in the direction of program control design, instruments, machine execution devices, etc., can solve the problems of no record of missing cache, no processing of reading, modifying and writing, etc., and achieve simple pipeline control Effect

Active Publication Date: 2015-10-14
HITACHI LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In addition, Patent Document 3 describes that the cache memory is multi-ported, and by dividing into a pipeline stage for fetching (reading) operands and a pipeline stage for writing operands, the data between memories can be efficiently executed. The method of the transmitted instruction, but it does not describe the action when the cache is missed (cache miss), or the action when the operand fetching and writing address compete, and it does not involve the processing of reading, modifying and writing at all.

Method used

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no. 1 Embodiment approach 》

[0047] figure 1 It is a figure which shows the internal structure and pipeline structure of the bit arithmetic processor with which the programmable controller which concerns on 1st Embodiment of this invention is equipped. also, Figure 13 In order to combine the pipeline structure related to the first embodiment with Figure 14 The figure shown by comparing the prior art. Such as figure 1 as well as Figure 13 As shown, the pipeline structure involved in this embodiment consists of (1) program counter (PC) stage, (2) instruction fetch (IF) stage, (3) decoding (D) stage, (4) memory read (R) stage , (5) operation execution (EX) stage, (6) memory writing (W) stage, consisting of six stages.

[0048] The PC stage includes an adder 102 that adds the value of the PC (Program Counter) 101 indicating the address of the immediately preceding instruction to a constant "1" or a designated register value, and selects a register value indicating the result of the addition or the br...

no. 2 Embodiment approach 》

[0071] Next, the data memory 20 in the first embodiment constituted by a cache memory (refer to figure 2 ) of the second embodiment of the present invention will be described. Figure 5 It is a diagram showing the configuration of the cache memory according to the second embodiment. Such as Figure 5 As shown, the cache memory 20A as the data memory 20 is a 2-way set associative (2way set associative) type cache memory, and is configured to include an address selector 201A, index (index) holding registers 221A and 222A, and a way (way) Selector 203, write data selector 204A, path 0 tag (tag) memory 205, path 1 tag memory 206, LRU (Least Recently Used) memory 207, path 0 data memory 208, path 1 data memory 209, hit determination circuit 210 , write-back control circuit 211 , path data selector 212 , and path holding registers 213 and 214 . figure 1 The address holding circuit 22 includes an address holding circuit 1 ( 22A) having index holding registers 221A and 222A, and ...

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Abstract

Provided is a programmable controller with which pipeline processing interrupts arising from read-modify-write operations, which occur frequently in programmable controllers comprising ladder language bit operation processors, are avoided. A pipeline stage (execution stage (EX)) which carries out bit operations and bit data merges is disposed after a pipeline stage (read stage (R)) which loads data subject to read-modify-write in a buffer register (141) and retains the address of the subject data in an address retention circuit (22), and thereafter, a pipeline stage (write stage (W)) which stores the merge result at the address that is retained at the read stage (R) is disposed.

Description

technical field [0001] The present invention relates to a programmable controller equipped with a bit arithmetic processor for high-speed sequence control of facilities such as iron and steel, electric power, water and water pipes, and various equipment. Background technique [0002] In programmable controllers, the prior art uses a ladder language that can express sequential control more efficiently. In the ladder language, in many cases, information represented by 1 bit, such as an open / closed state of a switch, is input, and information represented by 1 bit, such as a relay output, is output. Therefore, in order to execute the 1-bit data processing unique to the ladder language at high speed, the programmable controller is often equipped with a dedicated bit operation processor. [0003] The bit operation processor supports a dedicated instruction group suitable for processing 1-bit data, but since the destination for storing operation results is a general-purpose memory...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F12/08
CPCG06F9/30018G06F9/30043
Inventor 中三川哲明上胁正山田勉白石雅裕大谷辰幸
Owner HITACHI LTD