Input protection circuit
A technology for protecting circuits and input voltages, which is applied in the direction of emergency protection circuit devices, circuits, circuit devices, etc., and can solve problems such as the increase of leakage current that is difficult to allow and the influence of circuits
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no. 1 approach
[0037] Operation of the first embodiment
[0038] next to figure 1 The operation of the input protection circuit 10 of the first embodiment shown will be described in detail. When the input voltage Vin is within the power supply voltage range (VDD to VSS) of the voltage measurement circuit 1, the magnitude of the voltage between the gate and the source of the NMOSFET4 and PMOSFET5 becomes a predetermined voltage│Vs regardless of the input voltage Vin │. However, the predetermined voltage |Vs| is set to a minimum value for turning on the NMOSFET 4 and the PMOSFET 5 . Therefore, when the input voltage Vin is within the power supply voltage range (VDD-VSS), the NMOSFET4 and the PMOSFET5 are turned on. The voltage Vic is input to the voltage measurement circuit 1 through the NMOSFET4 and the PMOSFET5. As a result, the voltage measurement circuit 1 can measure the input voltage Vin with high precision.
[0039] When the input voltage Vin is higher than the positive power supp...
no. 2 approach
[0061] Operation of the second embodiment
[0062] next to figure 2 The operation of the input protection circuit 20 of the second embodiment shown will be described in detail. When the input voltage Vin is within the power supply voltage range VDD−Vs to VSS+2Vs, the voltage between the gate and the source of the PMOSFET 25 and the PMOSFET 26 is maintained at a predetermined value Vs. PMOSFET25 and PMOSFET26 are turned on to maintain a low resistance state. In this case, the voltage drop in PMOSFET25 and PMOSFET26 is small. Therefore, the output voltages V1 and V2 of the gate bias circuit 24 are applied to the gate terminals of the respective NMOSFET 4 and PMOSFET 5 at the same level. Thereby, the voltage between the gate and the source of NMOSFET4 and PMOSFET5 is also maintained at predetermined value Vs. NMOSFET4 and PMOSFET5 are turned on and maintained in a low resistance state. The input voltage Vin is input to the voltage measurement circuit 1 by turning on the NMO...
no. 3 approach
[0102] Operation of the third embodiment
[0103] next to Figure 6 and Figure 7 The operation of the input protection circuit 30 of the third embodiment shown will be described in detail.
[0104] First, the normal operation of the input protection circuit 30 will be described. The normal operation is the operation of the input protection circuit 30 when the input voltage Vin is within the range of the power supply voltage VDD−Vs to VSS+Vs of the voltage measurement circuit 1 . In this case, the voltage between the gate and the source of the PMOSFET 25 is maintained at a predetermined value Va. Therefore, PMOSFET 25 is turned on and maintains a low resistance state. Therefore, the voltage drop in PMOSFET 25 is small. Therefore, the output V1 of the gate bias circuit 34 is applied to the gate terminal of the NMOSFET 4 as it is. Therefore, the voltage between the gate and the source of the NMOSFET 4 is also maintained at the predetermined value Vs. Therefore, NMOSFET 4 ...
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