Field programmable gate array (FPGA) power-on reset system

Abstract

The invention discloses a field programmable gate array (FPGA) power-on reset system which comprises a power-on reset circuit and a reset signal detection circuit, wherein the power-on reset circuit is used for generating power-on reset (POR) pulse signals, the reset signal detection circuit is used for ensuring reset validity of the POR signals, and the power-on reset circuit is connected with the reset signal detection circuit. The power-on reset circuit transmits the POR pulse signals when voltage drain drain (VDD) of a chip first power supply rises to 1.6V, and the POR pulse signals are used for controlling resetting of an FPGA chip. By adopting the FPGA power-on reset system, the dynamic switching loss and short circuit power of the chip are reduced in the FPGA chip power on process, and safety and starting stability of the FPGA chip are improved.

Description

technical field [0001] The invention relates to the field of microelectronics, in particular to an FPGA power-on reset system. Background technique [0002] The problem of power dissipation in integrated circuits is a thermal problem. So all problems related to heat may lead to changes in chip power consumption. But in the natural environment, heat problem is one of the most common phenomena. These problems also exist for semiconductor integrated circuits. Energy in nature is always being transformed. After the chip is powered on, a lot of electric energy has to be converted into heat energy. For relatively small chips, this converted energy will not cause fatal damage to the chip. But for large-scale chips, such as CPU, GPU, FPGA, the problem of excessive power consumption is inevitable, and the huge heat will cause serious and irreversible damage to the chip. Moreover, with the continuous advancement of semiconductor process technology and the continuous reduction of ...

AI Technical Summary

Problems solved by technology

[0006] The existing FPGA power-on reset starts when the chip power reaches a stable state of 2.5V. During the power-on process of the FPGA chip, the dynamic switching power consumption and short-circuit power of the chip are relatively large.

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