Stressed channel FETs with source/drain buffers

Abstract

A method for forming a stressed channel field effect transistor (FET) having a source / drain buffer zone (501) comprising: forming two gate stacks (202 / 203) on the substrate (201) Etching a cavity (301) in the substrate; depositing a source / drain buffer material (401) in the cavity; etching the source / drain buffer material to form a channel region with the FET (502) an adjacent vertical source / drain buffer; and depositing a source in the cavity adjacent to and above the vertical source / drain buffer Electrode / drain stressor material (601).

Description

technical field [0001] The present disclosure relates generally to the field of semiconductor fabrication and, more particularly, to forming field effect transistor (FET) devices having stressed channel regions. Background technique [0002] Mechanical stress within a semiconductor device substrate can be used to tune device performance. For example, in silicon (Si) technology, the channel of a FET may be oriented along the {110} plane of silicon. In this arrangement, hole mobility is enhanced when the channel is under compressive stress in the direction of the film and / or under tensile stress in the direction normal to the channel, whereas when the silicon film is under compressive stress in the direction normal to the channel Electron mobility increases under tensile stress. Accordingly, compressive and / or tensile stresses may advantageously be induced in the channel region of a p-type FET (PFET) or n-type FET (NFET) to enhance the performance of such devices. [0003] ...

AI Technical Summary

Problems solved by technology

Although the channel stress increases with decreasing proximity of the stressor to the channel, the close proximity of the heavily doped source / drain stressor material to the FET channel results in an Deterioration of electrostatic properties

In particular, heavily doped source / drain materials in close proximity to the channel region can exacerbate short-channel effects and punch-through problems, and can also increase parasitic leakage, junction capacitance, and from band-to-band tunneling during FET operation. floating body effect

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