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Erasing method of split gate flash memory

A split-gate flash memory and control gate technology, which is applied in the field of memory, can solve the problems of fast degradation of the tunnel oxide layer and low durability of flash memory, and achieve the effects of reducing voltage stress, slowing down the degradation speed, and improving durability

Active Publication Date: 2017-08-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
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AI Technical Summary

Problems solved by technology

[0005] The present invention solves the problems that the tunnel oxide layer in the flash memory degenerates quickly and the durability of the flash memory is low

Method used

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  • Erasing method of split gate flash memory
  • Erasing method of split gate flash memory
  • Erasing method of split gate flash memory

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Embodiment Construction

[0022] As described in the background technology, when the split-gate flash memory is erased, the tunnel oxide layer in the split-gate flash memory is subjected to a relatively large voltage stress, which causes the degradation of the tunnel oxide layer, and then Reduces the endurance of the entire flash memory. The inventor of the technical solution provides a method for erasing a split-gate flash memory after research.

[0023] In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0024] figure 1 It is a schematic diagram of the cross-sectional structure of the split-gate flash memory involved in the present invention. refer to figure 1 , the split-gate flash memory includes: a semiconductor substrate 100 having a source region 200 and a drain region 300 arranged at intervals on the semiconduct...

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Abstract

The invention discloses a method for erasing a split gate type flash memory. The split gate type flash memory comprises a first control gate, a second control gate, a source region, a drain region and a word line. The method comprises the following steps of: applying a first negative voltage to the first control gate and the second control gate at the time between a first moment and a second moment; applying a second negative voltage to the first control gate and the second control gate at the time between the second moment and a third moment, wherein an absolute value of the second negative voltage is more than that of the first negative voltage and the time between the second moment and the third moment accounts for 10%-20% of the time between the first moment and the third moment; applying a positive voltage to the word line and a 0V voltage to the source region and the drain region at the time between the first moment and the third moment. According to the method provided by the technical scheme of the invention, the degradation speed of a tunnel oxide layer in the split gate type flash memory can be reduced and the durability of the split gate type flash memory can be improved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a method for erasing a divided-gate flash memory. Background technique [0002] As an integrated circuit storage device, flash memory (Flash Memory) is widely used in portable computers, mobile phones, digital music players, etc. in electronic products. Generally, flash memory can be divided into two types according to the gate structure of transistors constituting a memory unit: stacked gate flash memory and split gate flash memory. Among them, split-gate flash memory has been widely used because it effectively avoids over-erasing effect and has higher programming efficiency. [0003] The Chinese invention patent with the publication number CN101465161A provides a split-gate flash memory sharing a word line, and correspondingly provides methods for reading, programming and erasing the split-gate flash memory. When erasing the split-gate flash memory, the tunnel oxide layer in ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/14
Inventor 顾靖
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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