Method and device for testing trap density and position of gate oxide layer

A test method and trap density technology, applied in the direction of semiconductor/solid-state device test/measurement, etc., can solve the problems of not considering the trap density of pn junction and the lack of trap density test.

Active Publication Date: 2013-10-23
PEKING UNIV
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  • Abstract
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  • Application Information

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Problems solved by technology

[0004] However, the above-mentioned test methods only focus on the density of traps on the gate oxide layer interface of n-type and p-type MOS devices, and lack of de

Method used

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  • Method and device for testing trap density and position of gate oxide layer
  • Method and device for testing trap density and position of gate oxide layer
  • Method and device for testing trap density and position of gate oxide layer

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Embodiment 1

[0041] Such as figure 1 Shown, a kind of testing method of gate oxide layer trap density and position, comprises the following steps:

[0042] S1. A negative voltage is connected to the source terminal and the drain terminal, and the substrate terminal is grounded, so that the pn junction is forward biased;

[0043] S2. After the pn junction is forward-biased, connect the gate DC scanning voltage to the gate, and scan according to the method from negative voltage to positive voltage, so that the surface of the device is converted from an accumulation state to a weak inversion state; During the scanning process of the grid DC scanning voltage, the substrate end is measured to obtain the substrate current;

[0044] S3. Establishing a first I-V curve between the substrate current and the gate DC scanning voltage;

[0045]S4. Apply a fixed voltage to the gate, and then repeat steps S1 to S3 multiple times to obtain a plurality of second I-V curves of the substrate current and th...

Embodiment 2

[0072] A gate oxide layer trap density and position testing device, characterized in that it includes an n-type MOSFET and a corresponding p-type gate oxide capacitor, or a p-type MOSFET and a corresponding n-type gate oxide capacitor; the n-type MOSFET and its corresponding The corresponding p-type gate oxide capacitor and the junction of the p-type MOSFET and its corresponding n-type gate oxide capacitor form a pn junction.

[0073] As shown in Figure 3(a), taking the n-type gate oxide layer interface trap density test device as an example, the left side of the n-type test device is the n-type MOSFET device part, which is composed of n ＋ , p-well and gate constitute the source, substrate and gate of the test device of the present invention, and the right side of the test device is the p-type gate oxide capacitor part, which is composed of n ＋ , n-well and gate constitute the drain, substrate and gate of the device of the present invention, wherein the gate is shared, so that...

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Abstract

The invention provides a method and a device for testing trap density and position of a gate oxide layer, and relates to the technical field of quality and reliability testing of an MOS (Metal Oxide Semiconductor) device. The method comprises the following steps: S1, accessing negative voltage at a source end and a drain end, grounding at a substrate end, so that p and n nodes are forward bias; S2, after the p and n nodes are forward bias, accessing a grid direct-current scanning voltage at a grid, and scanning from negative voltage to positive voltage, so that the surface of the device becomes weak inversion state from accumulation state; measuring the substrate end during the scanning process so as to obtain substrate current; S3, establishing a first I-V curve of the substrate current and the grid direct-current scanning voltage; S4, applying a fixed voltage to the grid, repeating the steps S1 to S 3 for multiple times so as to obtain a plurality of second I-V curves; measuring the heights of bottoms of the second I-V curves so as to obtain the trap density of p and n nodes. According to the method and the device, the strap density of the p and no nodes can be measured and the positions of traps can be positioned, so that the design of the device is improved so as to reduce the traps.

Description

technical field [0001] The invention relates to the technical field of MOS device quality and reliability testing, in particular to a method and device for testing the trap density and position of a gate oxide layer. Background technique [0002] With the rapid development of semiconductor technology and the substantial increase in the integration of microelectronic chips, the design and processing level of integrated circuits has entered the nano-MOS era. As the core of MOS devices, the gate oxide layer plays a decisive role in the quality and reliability evaluation of MOS devices. The role of the interface trap density of the gate oxide layer is one of the very important indicators. The generation of traps at the interface of the gate oxide layer reduces the mobility of the device, leading to a decrease in the performance of the device. Therefore, it is very necessary to monitor the traps at the interface of the gate oxide layer during the process flow. [0003] The commo...

Claims

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Application Information

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IPC IPC(8): H01L21/66
Inventor 何燕冬韦超张钢刚张兴
Owner PEKING UNIV
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