Test method and device for gate oxide layer trap density and position

Abstract

The invention provides a method and a device for testing trap density and position of a gate oxide layer, and relates to the technical field of quality and reliability testing of an MOS (Metal Oxide Semiconductor) device. The method comprises the following steps: S1, accessing negative voltage at a source end and a drain end, grounding at a substrate end, so that p and n nodes are forward bias; S2, after the p and n nodes are forward bias, accessing a grid direct-current scanning voltage at a grid, and scanning from negative voltage to positive voltage, so that the surface of the device becomes weak inversion state from accumulation state; measuring the substrate end during the scanning process so as to obtain substrate current; S3, establishing a first I-V curve of the substrate current and the grid direct-current scanning voltage; S4, applying a fixed voltage to the grid, repeating the steps S1 to S 3 for multiple times so as to obtain a plurality of second I-V curves; measuring the heights of bottoms of the second I-V curves so as to obtain the trap density of p and n nodes. According to the method and the device, the strap density of the p and no nodes can be measured and the positions of traps can be positioned, so that the design of the device is improved so as to reduce the traps.

Description

Technical field [0001] The invention relates to the technical field of MOS device quality and reliability testing, in particular to a method and device for testing the density and position of gate oxide traps. Background technique [0002] With the rapid development of semiconductor technology and the substantial increase in the integration of microelectronic chips, the design and processing level of integrated circuits has entered the era of nano-MOS. As the core of MOS devices, the gate oxide layer plays an important role in the quality and reliability evaluation of MOS devices. Among them, the interface trap density of the gate oxide layer is one of the very important indicators. The generation of gate oxide layer interface traps reduces the mobility of the device, resulting in a decrease in device performance. Therefore, it is very necessary to monitor the gate oxide layer interface traps in the process flow. [0003] The commonly used gate oxide interface trap density test de...

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Problems solved by technology

[0004] However, the above-mentioned test methods only focus on the density of traps on the gate oxide layer interface of n-type and p-type MOS devices, and lack of density testing of traps near the interface, especially without taking into account the trap density of pn junctions and pn junction traps. The location distribution of

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