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Connection of a chip provided with through vias

By forming a through-hole structure in the chip and filling it with conductive materials and easily deformable insulating materials, the problem of deformation of connecting elements caused by the difference in expansion coefficient during the heating process of the three-dimensional integrated circuit structure is solved, and the reliability of the component is improved. and stability.

Active Publication Date: 2013-11-06
STMICROELECTRONICS FRANCE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when heating this assembly, lateral stresses are applied to the connecting elements 14 of the interconnection network 16, so these elements and the welds connecting them to the support and the insert plate risk cracking and altering the quality of the connection

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] It can be observed to form three-dimensional assemblies such as figure 1 At least one of the chips of the assembly substantially includes a through via. The chips to be considered are silicon interposer chips such as figure 1 The following description is given in the case of a board or chip 4, but it should be noted that the following can apply to any chip including vias that is interposed between other chips to which it is connected.

[0020] figure 2 yes figure 1 An enlarged cross-sectional view of a part of chip 4. In this example consider the case where vias are formed through this chip by using the following sequence of steps.

[0021] The upper chip surface is coated by an insulating layer 21 in which metal interconnection levels (not shown) are formed, at least one metallization 23 is arranged in front of the locations where vias are desired to be formed.

[0022] Openings are drilled from the lower surface of the chip which, if it is a highly thinned chip,...

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PUM

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Abstract

A chip provided with through vias wherein the vias are formed of an opening with insulated walls coated with a conductive material and filled with an easily deformable insulating material, elements of connection to another chip being arranged in front of the easily deformable insulating material.

Description

technical field [0001] This disclosure relates to the field of so-called three-dimensional integrated circuits, which include stacking of chips and other elements to provide interconnection and increase integration density. Background technique [0002] figure 1 An example of a three-dimensional structure intended to connect one or several semiconductor chips comprising an integrated circuit to a printed circuit board is shown. [0003] In this example, two integrated circuit chips 1 and 2 are shown assembled with an interposer 4 on a support 6 such as ceramic, polymer or part of a printed circuit board or the like. The lower surface of the support 6 supports connection elements, such as lugs 8 , which are intended to provide a connection with a step between them compatible with the size and position of the connection area of ​​the printed circuit board, not shown, The component must be assembled on and connected to these connection areas. [0004] Each chip 1, 2 comprise...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/532H01L23/488
CPCH01L21/486H01L23/147H01L2224/73204H01L2224/32145H01L2224/32225H01L21/76877H01L23/5384H01L23/49822H01L2224/16145H01L2224/16225H01L2224/16227H01L23/481H01L23/28H10W70/095H10W70/698H10W20/20H10W70/685H10W70/635H10W70/611H10W90/732H10W90/734H10W90/722H10W90/724H10W74/15H10W20/216H10W74/00H10W20/056
Owner STMICROELECTRONICS FRANCE