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Semiconductor Reflow Processing for High Aspect Ratio Fill

A high aspect ratio, conductive layer technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as difficult to fill, slow, and takes several hours

Active Publication Date: 2018-03-09
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

To avoid void formation and pinch-off in vias, traditional ECD filling in TSV vias is typically a slow process due to the amount of metal required to fill the TSV vias, sometimes taking hours to partially fill the vias, and Still proving difficult to fill due to void formation in vias

Method used

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  • Semiconductor Reflow Processing for High Aspect Ratio Fill
  • Semiconductor Reflow Processing for High Aspect Ratio Fill
  • Semiconductor Reflow Processing for High Aspect Ratio Fill

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Embodiment Construction

[0034] Embodiments of the present disclosure are directed to workpieces, such as semiconductor wafers, devices or processing components for processing the workpieces, and methods of processing the workpieces. The term workpiece, wafer or semiconductor wafer means any flat medium or object, including semiconductor wafers and other substrates or wafers, glass, masks and optical or storage media, MEMS substrates or any other artifacts.

[0035] The process described herein will be used for metal deposition or metal alloy deposition in high aspect ratio features of workpieces such as vias in through-silicon via (TSV) features. In embodiments of the present disclosure, TSV feature sizes according to embodiments of the present disclosure include in the range of about 0.5 microns to about 15 microns, in the range of about 0.5 microns to about 10 microns, or in the range of about 0.5 microns to about 10 microns. A diameter in the range of about 2 microns, and a depth in the range of ...

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PUM

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Abstract

Semiconductor reflow processing for high aspect ratio filling, a method for at least partially filling a feature on a workpiece comprising the steps of: obtaining a workpiece comprising a feature having an aspect ratio in the range of about 10 to about 80 width ratio; depositing a first conformal conductive layer in the part; and thermally treating the workpiece to reflow the first conformal conductive layer in the part.

Description

technical field [0001] The present disclosure relates to methods for electrochemically depositing conductive materials (such as Metals such as copper (Cu), cobalt (Co), nickel (Ni), gold (Au), silver (Ag), manganese (Mn), tin (Sn), aluminum (Al) and alloys of the above) Methods. Background technique [0002] TSV deposition is typically aimed at creating vertical interconnects through the workpiece for upper and lower connections to interconnects on other workpieces. In one non-limiting example of TSV integration, metal is deposited to fill the TSV vias, and then the backside of the wafer is ground until the bottoms of the vias are exposed, creating a second connection point for the vias. However, it should be understood that other types of TSV integrations are also within the scope of this disclosure. [0003] Typical TSV features have dimensions that may range in diameter from about 1 micron to about 15 microns and depths that may range in depth from about 20 microns to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L23/48
Inventor 伊斯梅尔·T·埃迈什罗伯特·C·林克
Owner APPLIED MATERIALS INC