[0018] Refer now figure 2 , Which shows a circuit diagram of an operational transconductance amplifier 200 with enhanced current sink capability.
[0019] figure 2 Similar reference numerals in figure 1 Similar parts shown. I won't repeat it here figure 2 In this category of parts, but refer to the previous reference figure 1 Provide a description.
[0020] The difference between the amplifier 200 and the amplifier 100 is that the second current source 134 has been replaced by the current sink circuit 202. The current sink circuit 202 includes a reference current source IC1, which is coupled to source current into a current mirror circuit 206 formed by transistors M4 and M5. The transistors M4 and M5 are n-channel type MOSFET transistors. The source terminals of the transistors M4 and M5 are coupled to the reference node 110. The drain terminal of the transistor M5 is coupled to receive the current sourced by the reference current source IC1. The gate terminals of the transistors M4 and M5 are coupled together and to the drain terminal of the transistor M5. The current from the reference current source IC1 is therefore reflected by the current mirror circuit 206 to the drain terminal of the transistor M4 according to the scale factor set by the relative sizes of the transistors M4 and M5.
[0021] The current sink circuit 202 further includes a pair of p-channel type MOSFET transistors M2 and M3. The source terminal of the transistor M3 is coupled to the positive input terminal IN+ of the amplifier 200. The source terminal of the transistor M2 is coupled to the output node 140. The gate terminals of the transistors M2 and M3 are coupled together and to the drain terminal of the transistor M3. Because the amplifier 200 is configured with a shunt connection 144 in a non-inverting unity gain buffer operation mode, the voltage at the output node 140 will generally be equal to the voltage at the positive input terminal IN+ of the amplifier 200. The transistors M2 and M3 are therefore used to mirror the current at the drain terminal of the transistor M2 (received from the current mirror 206) to the drain terminal of the transistor M2 according to the scale factor set by the relative size of the transistors M2 and M3.
[0022] The current sink circuit 202 further includes a resistor R1 that is coupled at an intermediate node V1 between the drain terminal of the transistor M2 and the reference node 110.
[0023] The current sink circuit 202 further includes an n-channel type MOSFET transistor M1, the gate terminal of which is coupled to the intermediate node V1. The drain terminal of the transistor M1 is coupled to the output node 140. The source terminal of the transistor M1 is coupled to the reference node 110. The circuit 202 is designed so that the size of the transistor M1 is customized to support the large current sink capability.
[0024] The circuit 202 serves to selectively activate the transistor M1 so as to better absorb the current I_sink when the current I_sink is applied to the output node 140. This selective activation is made in response to the circuit 202 sensing an unacceptable rise in the voltage at the output node 140 (caused by the applied current I_sink). When the applied current I_sink is zero, the circuit 202 is in sleep mode, in which the transistor M1 is turned off. In this case, the voltage at the intermediate node V1 is close to the reference node 110 voltage (for example, ground). When the voltage at the output node 140 is equal to the voltage at the positive input terminal IN+ of the amplifier 200, the operation of the sleep mode state is set by the bias circuit, which is routed to the reference current source IC1, the transistors M2-M5, and the resistor R1 is formed.
[0025] The increase in the current I_sink applied to the output node 140 results in a corresponding increase in the voltage at the output node 140. This increases the Vgs of transistor M2 and transistor M2 will conduct additional current accordingly. The increase in the current applied across the resistor R1 through the transistor M2 results in an increase in the voltage at the intermediate node V1. When the voltage at the intermediate node V1 rises above the threshold voltage of the transistor M1, the transistor M1 turns on and sinks current from the output node 140 to the reference node 110. The absorption of the current flowing through the transistor M1 causes the voltage at the output node 140 to decrease. As the voltage of the output node 140 decreases, the current flowing through the transistor M2 decreases and the voltage at the intermediate node V1 decreases, which in turn causes the transistor M1 to turn off. Those skilled in the art will therefore know that the circuit 202 is used to respond only to the peak value of the current I_sink applied to the output node 140. In all other cases, the circuit 202 is non-operational (that is, sleeping), and does not affect the operation of the amplifier circuit 200.
[0026] Refer now Figure 3A to Figure 3D , Which shows figure 2 Waveform diagram of the operation of the circuit.
[0027] Reference Figure 3A , Reference numeral 300 is the voltage at the positive input terminal IN+ of the amplifier 200, and reference numeral 302 is the voltage at the output node 140. Reference numeral 304 shows the operation of the amplifier circuit 200 in a non-inverting unity gain buffer configuration in which the output voltage 302 follows the input voltage 300. At time 306, the peak value of the sink current I_sink is applied to the output node 140. The peak current is shown in Figure 3B in. The peak value of the sink current I_sink causes a corresponding increase in the voltage 302 at the output node 140 (reference numeral 308). Current 202 wakes up from sleep mode and responds to voltage increase 308 by turning on transistor M1. Figure 3D It is shown that the voltage V1 at the gate terminal of the transistor M1 rises in response to the peak of the sink current I_sink. Figure 3C Shows due to increase Figure 3D The current 310 flowing through the transistor M1 is caused by the control voltage V1. The activation of the transistor M1 causes the current flowing through the transistor M1 to increase (reference numeral 312), which is used to sink the applied current I_sink and reduce the voltage 302 at the output node (reference numeral 314). As the voltage decreases 314, the circuit 202 turns off the transistor M1, and the discharge current decreases accordingly (reference numeral 316). Once the peak 308 of the voltage 302 at the output node 140 is processed due to the sink current I_sink, the circuit 202 resumes sleep mode and the operation of the amplifier in the non-inverting unity gain buffer configuration continues, where the output voltage 302 follows the input voltage 300.
[0028] The foregoing provides a comprehensive and informative description of some exemplary embodiments of the present invention through illustrative and non-limiting examples. However, in view of the foregoing description read in conjunction with the accompanying drawings and appended claims, various modifications and adaptations may become apparent to those skilled in the art. However, all these teachings and similar modifications of the present invention will still fall within the scope of the present invention defined by the appended claims.
