Device for verifying advanced microcontroller bus interface

Abstract

The invention discloses a device for verifying an advanced microcontroller bus interface. The device for verifying the advanced microcontroller bus interface comprises a parameter generating unit, a transmission unit, a drive unit, a detection unit and a functional coverage rate statistic unit. The parameter generating unit is used for generating a random transmission packet according to constraint conditions, wherein the transmission packet includes data, addresses, reading-writing types, burst length and other parameters. The transmission unit is used for generating different instructions according to the contents of the random transmission packet. The drive unit is used for converting the different instructions into interface signals and sending the interface signals to a verified object. The detection unit is used for monitoring behaviors of a bus of the verified object and checking the correctness of a bus protocol in real time. The functional coverage rate statistic unit is used for receiving the transmission packet sent by the transmission unit and / or the detection unit and performing coverage rate statistics to the behaviors of the bus according to the contents, including at least one of access type, address space, data space and burst type. The device is suitable for any system-level or module-level verification based on an advanced microcontroller bus architecture (AMBA) and can improve the design verification efficiency of a whole chip.

Description

technical field [0001] The invention relates to the technical field of system chips, in particular to the verification technology of system chips. The present invention relates to a device for verifying the bus interface of an advanced microcontroller. Background technique [0002] As leading system-on-chip (SoC, System on Chip) designs include more complex protocols, the intellectual property (VIP, Verification Intellectual Property) used for verification has become an important part of the verification environment and enables Engineers were able to meet coverage targets on tight project schedules. VIP provides various on-chip and off-chip functional models such as PCI Express, USB, MIPI, HDMI, Ethernet, etc. Verification engineers use these models to test all SoC interfaces prior to tapeout, enabling them to verify that an interface complies with published standards. [0003] The SystemVerilog Verification Methodology (VMM) introduced by electronic design automation (...

AI Technical Summary

Problems solved by technology

For the standards before AMBA3.0, there are related commercial VIPs, but most of them are based on related verification methodologies (or simulation work), and there is no VIP based solely on System Verilog language

[0007] In response to the need for higher performance and power efficiency, the industry is now seeing widespread and rapid adoption of AMBA 4AXI4 TM and ACE TM Protocol to support sustainable, diverse and multi-processor SoC chips. After the introduction of the AMBA 4.0 standard, there is no mature VIP to verify the bus interface of AXI4 and ACE. Therefore, it is necessary to develop a set of AMBA VIP, which is compatible with AMBA4 All standards below .0 have nothing to do with verification methodology or simulation tools. Based on the system verilog language, they can be integrated into any SoC verification environment of the AMBA system

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