Semiconductor device with air gap and method for fabricating the same

Abstract

A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming multiple layers of spacer layers with a capping layer interposed therebetween over the bit line structures, exposing a surface of the substrate by selectively etching the spacer layers, forming air gaps and capping spacers for covering upper portions of the air gaps by selectively etching the capping layer, and forming storage node contact plugs between the bit line structures.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2012-0058435 filed on May 31, 2012, the entire contents of which are hereby incorporated by reference. technical field [0003] Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device having an air gap and a method of manufacturing the same. Background technique [0004] In general, a semiconductor device includes a plurality of first conductive layer patterns and a plurality of second conductive layer patterns. Each second conductive layer pattern is formed between the first conductive layer patterns but insulated between the first conductive layer pattern and the second conductive layer pattern. The first conductive layer pattern may include gate electrodes, bit lines and metal lines. The second conductive layer pattern may include contact plugs, storage node contact plugs...

AI Technical Summary

Problems solved by technology

[0008] Since silicon oxide and silicon nitride layers still have high dielectric constants, there is a limit in reducing parasitic capacitance

Recently, some lower dielectric constant layers such as silicon boron nitride (SiBN) and silicon carbon nitride (SiCN) are being developed, but their dielectric constant is close to 6, which is still not low enough

Images