A storage method and device
A memory and control register technology, applied in the electronic field, can solve the problem of high hardware cost
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Embodiment 1
[0042] An embodiment of the present invention provides a storage method, such as figure 1 As shown, when the ADV7850 chip of the display is powered on, the method includes:
[0043] S101. The controller prohibits the display data channel DDC port of the display from accessing the SRAM of the ADV7850 chip.
[0044] The ADV7850 chip of the display includes a control register, a state register and an SRAM, and the present invention utilizes the SRAM space in the ADV7850 chip to write the EDID into the SRAM. When writing to EDID, it is necessary to disable the DDC port through the I 2 The C bus accesses the SRAM to prevent external devices from accessing the SRAM through the DDC port during the process of writing EDID, and at the same time ensure the correctness of writing EDID.
[0045] Specifically, the controller passes the I 2 The C bus writes an access prohibition command to the ADV7850 chip, so that the control register in the ADV7850 chip is set to 0.
[0046] S102. The...
Embodiment 2
[0060] An embodiment of the present invention provides a storage method, such as figure 2 As shown, when the ADV7850 chip of the display is powered on, the method includes:
[0061] S201. The controller prohibits the display data channel DDC port of the display from accessing the SRAM of the ADV7850 chip.
[0062] The ADV7850 chip of the display includes control registers, status registers and SRAM. When the ADV7850 chip is powered on, the chip performs a hardware reset by itself, that is, the contents of the control register, status register and SRAM are all cleared.
[0063] The present invention utilizes the SRAM space in the ADV7850 chip to write the EDID into the SRAM. In order to ensure the validity and correctness of the written EDID data and prevent external devices from accessing the SRAM through the DDC port, when writing the EDID, first prohibit the DDC port from passing through the I 2 The C bus accesses the SRAM.
[0064] Specifically, the controller passes t...
Embodiment 3
[0089] An embodiment of the present invention provides a controller, such as image 3 shown, including:
[0090] The processing unit 10 is used to prohibit the display data channel DDC port of the display from accessing the static random access memory (SRAM) of the ADV7850 chip, and the I of the display 2 The interface of the C bus is switched to the storage space of the SRAM for storing the external display device identification data EDID, so as to obtain the memory head address required for writing the EDID, and calculate the checksum of the EDID, if the calibration If the checksum is a preset value, the DDC port is enabled to access the EDID.
[0091] The storage unit 11 is configured to write the EDID according to the first address of the memory.
[0092] Further, the processing unit is specifically used to pass I 2 The C bus writes an access prohibition command to the ADV7850 chip, so that the control register in the ADV7850 chip is set to 0, by I 2 The C bus writes t...
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