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Pn-junction-free transistor with u-shaped tubular channel and method of manufacturing the same

A junction transistor, tubular technology, used in the field of VLSI manufacturing, can solve problems such as drop, achieve high performance, extend the actual length, and reduce the physical gate length.

Inactive Publication Date: 2015-12-02
SHENYANG POLYTECHNIC UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the physical channel length is further reduced to below 20nm, the ability of MOSFETs with multi-gate structure to overcome the short channel effect will be significantly reduced.

Method used

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  • Pn-junction-free transistor with u-shaped tubular channel and method of manufacturing the same
  • Pn-junction-free transistor with u-shaped tubular channel and method of manufacturing the same
  • Pn-junction-free transistor with u-shaped tubular channel and method of manufacturing the same

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] The method for manufacturing the above-mentioned non-PN junction insulated gate transistor with a U-shaped tubular channel is illustrated by taking an N-type channel as an example, and the steps are as follows:

[0044] Step 1, such as Figure 6 As shown, first provide an impurity concentration at 1×10 15 cm -3 ~5×10 19 cm -3 between N-type SOI wafers. The thickness of the silicon film on the surface of the N-type SOI silicon wafer is reduced.

[0045] Step 2, etch out such as Figure 7 The silicon film pattern shown, where two raised portions are used to form the vertical channel region.

[0046] Step 3, further etching out such as Figure 8 The silicon body 2 with a U-shaped tubular channel with three-dimensional structural features is etched away from step 2 to step 3 for the silicon dioxide insulating layer 3 formed in subsequent steps, the gate electrode 4 and between the device units The formation of the blocking dielectric layer leaves a space.

[0047] ...

Embodiment 2

[0051] In step 1, an impurity concentration of 2×10 18 cm -3 N-type SOI wafer, the surface silicon film thickness of N-type SOI silicon wafer is thinned, and other conditions are the same as embodiment one.

Embodiment 3

[0053] In step 1, an impurity concentration of 1×10 15 cm -3 N-type SOI wafer, the surface silicon film thickness of N-type SOI silicon wafer is thinned, and other conditions are the same as embodiment one.

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PUM

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Abstract

The invention discloses a non-PN junction transistor with a U-shaped tubular channel and a manufacturing method of the non-PN junction transistor. A silicon body of the U-shaped tubular channel with three-dimensional geometric features is formed above a wafer oxidation layer on the surface of an SOI wafer, a silicon dioxide insulating layer with three-dimensional geometric features is formed on the surface of the silicon body of the U-shaped tubular channel, a grid electrode with three-dimensional geometric features is formed on the surface of the insulating layer, and a source electrode and a drain electrode are respectively formed on the upper surfaces of vertical channels in both ends of the silicon body of the U-shaped tubular channel. Because the inner part of the silicon body of the U-shaped tubular channel has a uniform doping type, a PN junction does not need to be formed. The grid electrode is in a shape like the Chinese character ri by looking down from the surface of the wafer. The non-PN junction transistor has the advantages of high integration level, simple process and the like, is suitable for manufacturing deep nanoscale integrated circuits and is suitable for popularization and application.

Description

technical field [0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a structure of an SOI wafer-free PN junction-type insulated gate field-effect transistor with a three-dimensional U-shaped tubular channel suitable for the manufacture of ultra-high-integrated integrated circuits and its method of manufacture. Background technique [0002] When the channel length of traditional planar MOSFETs is reduced below 100 nanometers, the short channel effect will seriously affect its working performance. The MOSFET device based on the multi-gate structure, because the gate electrode acts on multiple directions of the channel region, makes the amount of free charges more effectively controlled, so compared with the traditional planar structure, it can better control the direction of the source / drain electric field. The penetration of the channel region partially suppresses the short channel effect caused by the reduced gate ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/10H01L21/336
CPCH01L29/1037H01L29/66477H01L29/78
Inventor 靳晓诗刘溪揣荣岩
Owner SHENYANG POLYTECHNIC UNIV