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Semiconductor package structure

A packaging structure and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problems of package warpage, thermal stress and unbalanced package structure.

Inactive Publication Date: 2014-01-15
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Another problem of the prior art is the warping phenomenon of the package body, which is mainly caused by thermal stress and imbalance of the package structure

Method used

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  • Semiconductor package structure
  • Semiconductor package structure

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Embodiment Construction

[0020] Hereinafter, the details of the implementation of the present invention will be described with reference to the accompanying drawings. The content of the accompanying drawings constitutes a part of the specification and is illustrated in a specific description manner that can implement the embodiment. The following embodiments have disclosed enough details to enable those skilled in the art to implement it. Of course, other embodiments can also be implemented in the present invention, or any structural, logical, and electrical changes can be made without departing from the embodiments described in the text. Therefore, the following detailed description is not intended to be regarded as a limitation, on the contrary, the embodiments contained therein will be defined by the claims.

[0021] figure 1 It is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present invention. Such as figure 1 As shown, the semiconductor pac...

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Abstract

A semiconductor package structure includes a package substrate having a first surface, a second surface opposite to the first surface, and a sidewall surface between the first surface and the second surface; a semiconductor device fixed to the first surface; and an upper mold cap that at least encapsulates the semiconductor device. The mold cap includes a vertical extension portion covering the sidewall surface and a horizontal extension portion covering a periphery of a solder ball implanting region on the second surface.

Description

Technical field [0001] The present invention relates to a packaging structure technology, in particular to a semiconductor packaging structure capable of reducing warpage and avoiding delamination. Background technique [0002] As those of ordinary skill in the art know, semiconductor integrated circuits are fabricated on semiconductor wafers using process steps such as thin film deposition, ion implantation, etching, and photolithography. After the integrated circuits on the wafer are completed, wafer testing and dicing are then performed, where the wafer dicing is usually performed with a dicing knife. The wafer is cut into individual chips, and then packaged with a packaging substrate or wafer carrier to form a package. In the packaging process, usually only the upper surface of the packaging substrate and the chips fixed on the upper surface are covered with a molded polymer resin. [0003] However, the disadvantage of the past practice lies in the internal delamination of th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/488
CPCH01L2224/4824H01L2224/73215H01L2224/48091H01L2224/73265H01L2224/32225H01L2924/15311H01L2924/1815H01L23/3128H01L23/13H01L23/49816H01L2924/181H01L2924/00014H01L2924/00H01L2924/00012
Inventor 林柏均
Owner NAN YA TECH